Apparatus including an overlay mark and method of producing semiconductor assembly

A technology for alignment marks and semiconductors, applied in semiconductor devices, semiconductor/solid-state device manufacturing, electric solid-state devices, etc., can solve problems such as small geometric size, chip failure, and unsatisfactory aspects, and achieve alignment precision And the effect of accuracy and chip yield improvement
CN102087488AActive Publication Date: 2011-06-08TAIWAN SEMICON MFG CO LTD
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Patent Information

Authority / Receiving Office
CN · China
Current Assignee / Owner
TAIWAN SEMICON MFG CO LTD
Publication Date
2011-06-08

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Abstract

The present invention provides an apparatus that includes an overlay mark and a method of producing a semiconductor assembly. The overlay mark includes a first portion that includes a plurality of first features. Each of the first features have a first dimension measured in a first direction and a second dimension measured in a second direction that is approximately perpendicular to the first direction. The second dimension is greater than the first dimension. The overlay mark also includes a second portion that includes a plurality of second features. Each of the second features have a thirddimension measured in the first direction and a fourth dimension measured in the second direction. The fourth dimension is less than the third dimension. At least one of the second features is partially surrounded by the plurality of first features in both the first and second directions.
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Description

technical field

[0001] The invention relates to a semiconductor component, in particular to an alignment mark used in a photoetching process. Background technique

[0002] The semiconductor integrated circuit (IC) industry has experienced rapid growth. Technological improvements in IC materials and design have spawned many generations of ICs, each with smaller and more complex circuits than the previous generation. However, these improvements also increase the complexity of the process and the complexity of manufacturing the IC, and similar developments in IC process and manufacturing are necessary for these improvements to be realized. During the evolution of integrated circuits, functional density (ie, the number of interconnected components per chip area) generally increases while geometry size (ie, the smallest component (or line) created using a fabrication process) decreases.

[0003] Small geometries set stricter requirements in the photolithographic etch process. ...

Claims

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