Initialization method of memory element

Abstract

The invention provides an initialization method of a memory element, comprising a step of transmitting at least N+1 clock periods to the memory element, wherein N represents the digit of a serial data output by the memory element. One of the clock periods is used for transmitting a first commencement and termination signal to the memory element. The other one of the clock periods is used for transmitting a second commencement and termination signal to the memory element.

Description

technical field [0001] The invention relates to a two-wire transmission interface, and in particular to an initialization method of a memory element with a two-wire transmission interface. Background technique [0002] General two-wire transmission interface, such as the bus between integrated circuits (Inter-integrated Circuit Bus, I 2 C Bus) uses two lines of serial clock (serial clock, SCL) and serial data (serial data, SDA) to transmit data. Taking liquid crystal display (LCD) as an example, its timing controller can use I 2 C to access electrically erasable programmable read-only memory (electrically erasable programmable read-only memory, EEPROM). The timing controller provides SCL to the EEPROM to synchronize the communication timing of each other. The data transmission between the timing controller and the EEPROM only depends on the SDA bus. The timing controller must pass the I 2 C to access the relevant setting data in the EEPROM. [0003] figure 1 is the de...

AI Technical Summary

Problems solved by technology

[0006] However, in the above reading procedure, the timing controller may interrupt the reading of the EEPROM due to the glitch of the reset signal or other factors.

When the timing controller re-reads the EEPROM program, the EEPROM may stop in an uncontrollable state due to the abnormal interruption of the previous reading program, thus causing the timing controller to be unable to read again

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