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Systems and methods for calibrating the loop bandwidth of a phase-locked loop (PLL)

A loop bandwidth, phase-locked loop technology, applied in the field of signal processing, can solve problems such as PLL loop bandwidth variation, PLL stabilization time and noise performance degradation

Inactive Publication Date: 2014-05-21
QUALCOMM INC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0005] However, there may be large variations in the loop bandwidth of the PLL
Also, PLL settling time and noise performance can be severely degraded

Method used

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  • Systems and methods for calibrating the loop bandwidth of a phase-locked loop (PLL)
  • Systems and methods for calibrating the loop bandwidth of a phase-locked loop (PLL)
  • Systems and methods for calibrating the loop bandwidth of a phase-locked loop (PLL)

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Embodiment Construction

[0018] Phase-locked loop (PLL) systems are used in both analog and digital circuits. These systems can include a phase-frequency detector (PFD), a charge pump, and a voltage-controlled oscillator (VCO) connected in a feedback configuration. The VCO produces the output signal of the PLL, and the various components of the PLL may cooperate to cause the output signal to tend to and eventually lock to a desired output frequency based on the frequency of a reference signal applied as input to the PFD. For example, a PLL system may be configured to generate an output signal with the same frequency as the input signal, or an output signal with an output frequency that is x / y times the input frequency.

[0019] The PLL is an electronically controlled system that also produces an output signal (Fout) that has a fixed relationship to the phase of an input reference signal (Fref). Thus, the output signal of the PLL circuit may correspond to both the frequency and the phase of the input ...

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Abstract

A method for calibrating the loop bandwidth of a phase-locked loop (PLL) is described. At least one resistor in the PLL filter is tuned in accordance with the frequency of an input reference signal. One or more capacitors in the PLL filter are tuned in accordance with the frequency of the input reference signal. Output pulses of one or more voltage controlled oscillators (VCO) are counted. A first charge pump current associated with a target loop bandwidth is counted in accordance with the counted output pulses. A programmable charge pump current is tuned to the calculated first charge pump current.

Description

technical field [0001] The present invention relates generally to signal processing and techniques related to signal processing. More specifically, the present invention relates to systems and methods for calibrating the loop bandwidth of a phase locked loop (PLL). Background technique [0002] Phase locked loop (PLL) frequency synthesizers can be used as building blocks in many types of systems such as audio and video processing systems, communication systems, and in other systems such as processing systems. A PLL is a device that generates an output signal with an output frequency that varies with the frequency of a reference signal. When a PLL is implemented in a device, the frequency of an output signal may change frequently. For example, the frequency of the output signal may change when the device is powered on or when the device changes from one channel to another. [0003] A PLL may contain certain components connected in a feedback loop. For example, a PLL may i...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H04L7/00H03L7/18
CPCH03L7/0898H03L7/093H03L7/107H03L7/18H03L7/1072
Inventor 朴程宏
Owner QUALCOMM INC