Method for manufacturing FinFET (field effect transistor)

Abstract

The invention discloses a method for manufacturing a FinFET (field effect transistor). The method comprises the following steps: generating a dielectric strip on a substrate; taking the dielectric strip as a mask to implant ions to form amorphous layers on the surface of the substrate; generating an amorphous semiconductor layer covering the dielectric strip on the substrate and carrying out thermal annealing on and recrystallizing the amorphous semiconductor layer to form a single crystal semiconductor layer; correspondingly processing the two ends, which are pre-designed as source / drain regions, of the dielectric strip to form source / drain regions; forming recrystallized semiconductor side walls at the two sides, which do not contact with the source / drain regions, of the dielectric strip; removing the dielectric strip between the side walls to form Fin bodies; generating sacrifice layers on the substrate and the Fin bodies, forming protective side walls at the two sides of the Fin bodies and oxidizing the Fin bodies to isolate the Fin bodies from the substrate; and removing the protective side walls and the sacrifice layers to form gate dielectric layers and gate electrodes. Themethod has the following beneficial effect: the thickness of the Fin bodies manufactured by the method can be controlled according to the actual requirements, so the method is especially suitable formanufacturing the transistors with higher requirement for the size of the Fin bodies.

Description

technical field [0001] The invention relates to the technical field of semiconductor integrated circuits and its manufacture, in particular to a manufacturing method of a FinFET transistor (fin-shaped field effect transistor). Background technique [0002] The improvement of integrated circuit performance is mainly achieved by continuously shrinking the size of integrated circuit devices to increase its speed. Currently, the feature size of integrated circuit devices (MOSFETs) has shrunk down to the nanometer scale. At this scale, various basic and practical limitations begin to appear, making the development of integrated circuit technology based on silicon planar CMOS technology encounter unprecedented challenges. It is generally believed that after hard work, CMOS technology may still advance to the 20nm or even 10nm technology node, but after the 20nm node, it will be difficult for the traditional planar CMOS technology to further develop. In recent years, among variou...

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Problems solved by technology

Due to the poor uniformity and repeatability of the geometric dimensions of the formed graphics, this technology cannot be used in the production of circuits.

Although spacer image transfer is a simple nano-scale processing technology that can be used to make a single device, this technology will produce many parasitic patterns, so it cannot be used in the production of circuits.

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