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Method of manufacturing semiconductor devices

A technology for semiconductors and devices, applied in the field of manufacturing semiconductor devices that can prevent pattern tilting, and can solve problems such as low reliability and electrical performance deterioration of flash memory devices

Inactive Publication Date: 2011-07-27
SK HYNIX INC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

Therefore, the electrical performance of the flash memory device may deteriorate, resulting in its low reliability

Method used

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  • Method of manufacturing semiconductor devices
  • Method of manufacturing semiconductor devices
  • Method of manufacturing semiconductor devices

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Embodiment Construction

[0029] Hereinafter, exemplary embodiments of the present specification will be described in detail with reference to the accompanying drawings. The drawings are provided to enable those of ordinary skill in the art to make and use the exemplary embodiments of the description.

[0030] Figure 2A to Figure 2G is a cross-sectional view illustrating a method of manufacturing a semiconductor device according to an exemplary embodiment of this specification.

[0031] refer to Figure 2A , an etch target layer 102 , a first auxiliary layer 104 , a second auxiliary layer 106 and a photoresist pattern 108 are sequentially formed on the semiconductor substrate 100 . The etch target layer 102 may be formed of an insulating layer, a conductive layer, or a stack of an insulating layer and a conductive layer. For example, in the case where the etch target layer 102 is used to form a gate of a flash memory device, the etch target layer 102 may be formed by stacking a tunnel insulating la...

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Abstract

A method of manufacturing semiconductor devices comprises forming an etch target layer and auxiliary patterns over a semiconductor substrate, forming spacers on sidewalls of the auxiliary patterns, removing the auxiliary patterns, performing an etch process to change both corners of upper portions of the spacers to be symmetrical to one another, and patterning the etch target layer by using the spacers.

Description

[0001] Cross References to Related Applications [0002] This application claims priority from Korean Patent Application No. 10-2009-0134120 filed on December 30, 2009, the entire contents of which are incorporated herein by reference. technical field [0003] Exemplary embodiments of the present invention relate to a method of manufacturing a semiconductor device, and more particularly, to a method of manufacturing a semiconductor device capable of preventing a pattern tilt phenomenon. Background technique [0004] A semiconductor device includes a plurality of gate patterns and metal lines. With the trend of high integration of semiconductor devices, the width and pitch of patterns, including gate patterns and metal lines, are gradually reduced. [0005] In order to facilitate the formation of patterns having narrow widths while improving the integration of semiconductor devices as described above, a patterning process using spacer technology has been introduced. [0006...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L21/033H01L21/8239H01L21/28H10B12/00H10B99/00
CPCH01L21/28132H01L27/11521H01L21/0337H01L21/28273H01L29/40114H10B41/30H10B99/00H10B12/00
Inventor 安明圭
Owner SK HYNIX INC