Verifying environment patterned chip verifying method and device

Abstract

The invention discloses verifying environment patterned chip verifying method and device, and relates to the field of electronic design automation (EDA) verification in a chip designing process. The method comprises the following steps: establishing a new test sample, grouping test points according to functions, automatically generating an input document required by chip verification in a patterning mode, and configuring parameters of a simulator; running the test sample, directly interacting with the simulator, and displaying encoding and simulating information of the simulator in a graph mode; observing the test result, verifying the next test sample if the test is successful; and performing regression testing after codes are modified if a fault sample is found. By utilizing the method,the patterning operation and management of chip verification can be realized, the time spent in studying new verification language by testing staff is saved, and the chip verification process becomessimple and intuitive, so that the studying cost of the testing staff is reduced, the chip verification period is greatly shortened, and the efficiency of chip verification is improved.

Description

technical field [0001] The invention relates to the field of EDA (Electronic Design Automation, electronic design automation) verification in the chip design process, in particular to a chip verification method and device with a graphical verification environment. Background technique [0002] At present, the functional verification of integrated circuits accounts for about 60%-70% of the investment in the entire chip development process, which is one of the keys to the success of the project and a very important part of the entire chip design process. In the design of integrated circuit chips, verification is one of the most complex and time-consuming links in the chip design process, and with the rapid development of microelectronics technology, the scale of ASIC (Application Specific Integrated Circuit, application specific integrated circuit) is increasing The larger the chip, the size of a chip is usually around several million gates or even tens of millions of gates. S...

AI Technical Summary

Problems solved by technology

[0004] At present, many chip verification platforms in the industry need to rely on chip testers to manually write test cases, and run all test cases by keeping in mind a large number of command lines. There is no systematic operation for the management and maintenance of test cases, which is very inconvenient. It is conducive to the regression test of the test case, and after the test case is run, the tester needs to check and analyze the simulation results by himself, which is very inconvenient

For the functional verification of large chips, the above factors make the functional verification of the chip extremely complicated and cumbersome, thus prolonging the chip development cycle, the efficiency of chip verification is low, and the operating cost of testers is high

Images