Verifying environment patterned chip verifying method and device

A technology of verification environment and verification method, which is applied in the field of chip verification method and device with graphic verification environment, can solve the problem of no systematic operation of test case management and maintenance, complex and cumbersome chip function verification, unfavorable test case regression test and other issues to achieve the effect of shortening the chip verification cycle, reducing learning costs, and reducing learning costs
CN102156784BActive Publication Date: 2013-01-02FENGHUO COMM SCI & TECH CO LTD
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Patent Information

Authority / Receiving Office
CN ยท China
Patent Type
Patents(China)
Current Assignee / Owner
FENGHUO COMM SCI & TECH CO LTD
Publication Date
2013-01-02

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Abstract

The invention discloses verifying environment patterned chip verifying method and device, and relates to the field of electronic design automation (EDA) verification in a chip designing process. The method comprises the following steps: establishing a new test sample, grouping test points according to functions, automatically generating an input document required by chip verification in a patterning mode, and configuring parameters of a simulator; running the test sample, directly interacting with the simulator, and displaying encoding and simulating information of the simulator in a graph mode; observing the test result, verifying the next test sample if the test is successful; and performing regression testing after codes are modified if a fault sample is found. By utilizing the method,the patterning operation and management of chip verification can be realized, the time spent in studying new verification language by testing staff is saved, and the chip verification process becomessimple and intuitive, so that the studying cost of the testing staff is reduced, the chip verification period is greatly shortened, and the efficiency of chip verification is improved.
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Description

technical field

[0001] The invention relates to the field of EDA (Electronic Design Automation, electronic design automation) verification in the chip design process, in particular to a chip verification method and device with a graphical verification environment. Background technique

[0002] At present, the functional verification of integrated circuits accounts for about 60%-70% of the investment in the entire chip development process, which is one of the keys to the success of the project and a very important part of the entire chip design process. In the design of integrated circuit chips, verification is one of the most complex and time-consuming links in the chip design process, and with the rapid development of microelectronics technology, the scale of ASIC (Application Specific Integrated Circuit, application specific integrated circuit) is increasing The larger the chip, the size of a chip is usually around several million gates or even tens of millions of gates. S...

Claims

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