32results about How to "Reduce testing overhead" patented technology

The invention discloses a method and an apparatus for a test in a joint development mode. The method comprises: obtaining a new main code, wherein updated branch codes are combined into a main code to generate the new main code; starting a compiling tool to compile the new main code; monitoring whether an installation package is generated in a compiling process of the new main code or not, and if the installation package is monitored, obtaining the installation package and/or a reference package before the updated branch codes are combined into the main code; and performing an automated test on the installation package and/or the reference package to generate an automated test result. According to the method and the apparatus, the technical problems of inaccurate test result and low test efficiency caused by adoption of a timed test method in a software development mode of combining branch codes with a main code in the prior art are solved.

The invention provides a crowdsourcing test method. The crowdsourcing test method comprises the following steps: a test client side is used for sending characteristic information of the test client side to a test server; the test server is used for selecting a to-be-tested client side used for executing to-be-tested service according to the received characteristic information of at least one test client side; the test server is used for sending a to-be-tested service list to the to-be-tested client side; the to-be-tested client side is used for testing the to-be-tested service in the to-be-tested service list to obtain a test result of the to-be-tested service; and finally, the to-be-rested client side is used for sending the test result to the test server. The crowdsourcing test method used for testing network application service is used for remarkably improving the test result and effectively reducing the test cost.

The present invention relates to an integrated circuit test system. The integrated circuit test system comprises an automatic test unit, a test interface unit and an on-chip test unit embedded in a to-be-tested chip, the on-chip test unit comprises an access selection module, a sampling holding module and a calibration module, and the to-be-tested chip is connected with the automatic test unit via the test interface unit. The automatic test unit generates a test vector and an access control signal and transmits to the test interface unit, the access selection module receives the access control signal adapted by the test interface unit and outputs an access selection signal to the sampling holding module or the calibration module based on the access control signal. According to the present invention, the test of the high speed (GHz) to-be-tested chip is realized, in addition, by just needing the test interface unit to finish the electrical connection of the automatic test unit and the to-be-tested chip, the integration of the to-be-tested chip and a conventional integrated circuit test flow is realized, thereby improving the test efficiency and reducing the test cost.

The invention discloses a method and a system for determining an execution sequence of a test case suite. The method comprises the steps as follows: the single case switching cost between any two test cases in an initial test case suite is calculated; h test cases with all combination possibilities are selected from the initial test case suite, and all the possible first optimum execution sequences and first switching costs which are formed by the h test cases are obtained; according to the first switching costs and the single case switching cost, all possible second optimum execution sequences and second switching costs which are formed by h+1 test cases are calculated and obtained; the second optimum execution sequences and the second switching costs are taken as the first optimum execution sequences and the first switching costs respectively, h is increased by 1, a previous step is returned until the second optimum execution sequences comprise all test cases; and a second optimum execution sequence with the smallest second switching cost is taken as the optimum execution sequence, so that minimum reconfiguration times of parameters in a test can be realized, and the expenditure is reduced.

The invention provides a testing device for a memory chip in a hybrid circuit. capable of achieving fault positioning and diagnosis at the same time; The device comprises a built-in self-test circuitand a bus multiplexing circuit. The built-in self-test circuit and the bus multiplexing circuit are arranged on the main control protocol chip; The built-in self-test circuit is connected with a selection signal port of the bus multiplexing circuit. The built-in self-test circuit is connected with the bus multiplexing circuit through the test mode control bus, the test mode address bus and the test mode data bus. The main control protocol chip also comprises a functional memory controller; Wherein a control bus of the main control protocol chip is connected with a control port of the memory chip, a data bus of the main control protocol chip is connected with a data port of the memory chip, and an address bus of the main control protocol chip is connected with an address port of the memorychip; An output data bus of the main control protocol chip is connected with an output data port of the memory chip; And the built-in self-test circuit and the functional memory controller read data on the memory chip through the output data bus.

The invention provides an interface test case generation method and device, and the method employs different combination strategies for different parameter input domains, employs an orthogonal array method for the normal test data to generate a pairwise-covered normal test case set, and achieves the verification of the normality of a to-be-tested interface to the maximum degree through employing fewer resources. A single-coverage abnormal test case set is generated by adopting a basic selection method for abnormal test data, so that an abnormal source can be determined, and sharp increase of the number of test cases can be avoided. According to the scheme, good test coverage is obtained, the test overhead is greatly reduced, and the interface test efficiency is effectively improved.

The invention relates to a method for testing dispatching of an on-chip systematic embedded logical core by a multistage order algorithm. The operation method comprises the following steps of: establishing and initializing a dispatching matrix Z; line expanding the dispatching matrix Z; line contracting the dispatching matrix X; two-dimensionally dispatching and sequencing the total testing band width to the total testing time (W-T) of the dispatching matrix Z; double-traversing a total testing band width-adjusting factor (W-alpha) of the dispatching matrix Z; and generating a report. The invention is capable of effectively and integrally solving the two independently problems of the test dispatching of the on-chip systematic embedded logical core and the test link chaining in the logical core, thereby effectively reducing the testing time and testing cost of the on-chip system. The method is convenient in operation, and is applicable to various on-chip systems for finishing the measurability design of the logical core by scanning chain.

The invention discloses a super-sampling light ray tracking method for reusing scene point light source visibility. According to the method, when oversampling light ray tracing drawing is carried outon a three-dimensional scene; scene points which cannot be directly seen from a viewpoint on a light transmission path are detected; the light source visibility is tested; Firstly, whether scene points adjacent to the grid space data structure exist in a certain range or not is searched for in the grid space data structure; if not, the visibility between the light source and the currently processed scene point is calculated and stored in the grid space data structure, and otherwise, the light source visibility of the nearest scene point in the space position and the normal vector is used as alight source visibility approximate value of the currently processed scene point. According to the method, the light source visibility test expenditure in the super-sampling light ray tracing and drawing can be remarkably reduced, and the speed of the three-dimensional scene super-sampling light ray tracing and drawing is increased.

The invention relates to a three-step sign test method combined with odd-even check. Test steps of the three-step sign test method combined with the odd-even check comprise that step 1, the corresponding boolean expression of a circuit is read from a text; step 2, the boolean expression is analyzed to generate corresponding intermediate data and the odd-even check is conducted; step 3 based on a foundation of the odd-even check, a first step sign test judgment, a second step sign test and a third step sign test judgment are conducted according to the intermediate data correspondingly generated; step 4, a test result is recorded in a textual mode. The three-step sign test method combined with the odd-even check has the advantages of improving test efficiency and a failure coverage rate of the sign test simultaneously and enabling a former circuit not capable of testing a sign to be capable of conducting the sign test. The three-step sign test method combined with the odd-even check brings in the odd-even test based on a traditional sign test in the first place, preprocesses the circuit being tested, improves test efficiency, conducts further sublimation process on the sign test to form the second step sign test and the third step sign test, and improves the failure coverage rate of the test.

The invention provides a three-dimensional chip testing method and a three-dimensional chip testing device. The three-dimensional chip testing device comprises a first feature analyzer, a second feature analyzer and a third feature analyzer, wherein the first feature analyzer arranged on a first-layer chip is connected with the first-layer chip, a second-layer chip and a third-layer chip and is used for testing a three-dimensional chip to obtain a first testing result; the second feature analyzer arranged on the second-layer chip is used for testing the second-layer chip to obtain a second testing result; the third feature analyzer arranged on the third-layer chip is used for testing the third-layer chip to obtain a third testing result. The three-dimensional chip is a chip formed by binding of the first-layer chip, the second-layer chip and the third-layer chip. The three-dimensional chip testing method and the three-dimensional chip testing device have the advantages that testing of each chip before binding and the three-dimensional chip obtained after binding of the chips is achieved; the feature analyzers for chip testing are arranged inside the three-dimensional chip, so that the chips can be detected in real time, storage of a great number of data is unneeded, storage capacity is reduced and testing overheads are lowered.

The invention discloses a method of testing the speed of data transmission from PCI Express equipment to a host on the basis of FPGA (field programmable gate array). The method includes the steps of S1, modifying an FPGA transmission layer, adding a speed measurement code, for the speed of data transmission between test equipment and the host, into the FPGA transmission layer; S2, setting an equipment writing performance counter; S3, allowing the speed measurement code to read a counted value of the equipment writing performance counter, and calculating the speed of data transmission from the equipment to the host according to the equation: S=V/(C/H)=V*H/(C/(P-1)*P). The method has the advantages that testing accuracy is high, measuring speed is high, testing objectivity is high, and testing cost is low.