32results about How to "Reduce testing overhead" patented technology

The invention discloses an integrated circuit device neural network modeling sample selecting method and device. With respect to an input variable with a biggest mean impact value, by continually equally diving an interval of the input variable, equal division actions stop until relative errors of all divided intervals are equal to or less than preset error precision, and the length of the divided interval with a smallest length is the step length of the output variable, then step length of each of other input variable is calculated respectively according to the step length of the input variable, finally, with respect to each input variable, points are got according to a change interval and a step length to obtain sample points assembly of each input variable, thus selection of low sample data amount can be achieved under the condition of given precision, and the low sample data amount further saves testing expenditures needed by element molding and increase the training speed of the neural network.

The invention discloses a method and an apparatus for a test in a joint development mode. The method comprises: obtaining a new main code, wherein updated branch codes are combined into a main code to generate the new main code; starting a compiling tool to compile the new main code; monitoring whether an installation package is generated in a compiling process of the new main code or not, and if the installation package is monitored, obtaining the installation package and / or a reference package before the updated branch codes are combined into the main code; and performing an automated test on the installation package and / or the reference package to generate an automated test result. According to the method and the apparatus, the technical problems of inaccurate test result and low test efficiency caused by adoption of a timed test method in a software development mode of combining branch codes with a main code in the prior art are solved.

The invention relates to an integrated circuit testing system, which includes an automatic testing unit, a testing interface unit, and an on-chip testing unit embedded on a chip to be tested. The on-chip testing unit includes a channel selection module, a sampling and holding module, and a calibration module. The above-mentioned test interface unit is connected with the automatic test unit, and the automatic test unit generates test vectors and path control signals and transmits them to the test interface unit; the path selection module receives the path control signals transferred by the test interface unit, and based on the path control signals to the sampling The hold module or the calibration module outputs a channel selection signal. The present invention realizes the test to the high-speed (such as GHz) chip to be tested; In addition, only the test interface unit is required to complete the electrical connection between the automatic test unit and the chip to be tested, so as to realize the integration of the chip to be tested and the existing integrated circuit test process, thereby improving Improve test efficiency and reduce test overhead.

The invention discloses verifying environment patterned chip verifying method and device, and relates to the field of electronic design automation (EDA) verification in a chip designing process. The method comprises the following steps: establishing a new test sample, grouping test points according to functions, automatically generating an input document required by chip verification in a patterning mode, and configuring parameters of a simulator; running the test sample, directly interacting with the simulator, and displaying encoding and simulating information of the simulator in a graph mode; observing the test result, verifying the next test sample if the test is successful; and performing regression testing after codes are modified if a fault sample is found. By utilizing the method,the patterning operation and management of chip verification can be realized, the time spent in studying new verification language by testing staff is saved, and the chip verification process becomessimple and intuitive, so that the studying cost of the testing staff is reduced, the chip verification period is greatly shortened, and the efficiency of chip verification is improved.

The invention discloses a regression test case reusing method based on a software combination test. The method mainly includes the following steps that all combinations needing to be covered of a new model are calculated; an attempt is made reuse each existing test case, if each test case can be reused, the test case is converted into a test case under the new model and added to a test case set, the combination covered with the test case is removed, or otherwise, the test case can not be reused and is abandoned; if combinations which are not covered exist, new test cases are used for supplementation according to a traditional combination test generation method, the remaining combinations which are not covered are covered, and the new test cases are added to a new test case set; finally, the acquired test case set is a regression combination test case set reusing the existing test cases.

The invention relates to a method for determining the performance of a Web server. Performance evaluation cannot be performed on a real server by the conventional method. In the method provided by the invention, a peak load of the web server is determined by monitoring the usage rate of internal memories and central processing units (CPU) of the Web server and a host and the response time and an error rate of a user request and by analyzing a relationship between the usage rates and a user request capacity, a relationship between the response time and the user request capacity, and a relationship between the error rate and the user request capacity, so that the performance of the Web server is evaluated rapidly and correctly, and a correct and reliable basis for using hardware resources reasonably and effectively and meeting a user requirement is provided. By the method, the maximum real utilization ratio of a proper reference resource is selected as a reference point to calculate the next user request capacity, and the request capacity obtained through calculation is smaller than the peak load capacity of the server no matter whether the resource is a performance bottleneck of the Web server.

The invention discloses a software testing method, which is applied to a testing server in a testing platform. The testing platform also includes several testing hosts. The method includes the following steps: receiving a testing request for target software; determining a testing task according to the testing request Information, the test task information includes at least the information of the test network, the information of the test host in the test network, the information of the test scene and the information of the test case script corresponding to each test task; according to the test task information, each test Tasks are assigned to corresponding test hosts, so that each test host executes corresponding test tasks. By applying the technical solution provided by the embodiment of the present invention, the test server assigns each test task to a corresponding test host according to the test task information to complete the test task, which can reduce the software test cost and shorten the product development cycle. The invention also discloses a software testing device, which has corresponding technical effects.

The invention discloses an embedded boundary scan data compression and synthesis method and device. The method comprises the steps of: obtaining a standard scan chain data; obtaining a pin data used in the test, a test matrix and a response matrix; storing the standard scan chain data, the pin data used in the test, the test matrix and the response matrix into the chip of the embedded test device; obtaining the standard scan chain data, the pin data used in the test, the test matrix and the response matrix stored in the chip; calculating the position of the scan unit on the standard scan chain data of each pin used in the test to use the vector synthesis standard scan chain data in the test matrix and the vector synthesis standard scan chain data in the response matrix. The method and device effectively solves the problems of small storage space and being unable to conduct the boundary scan test of a large quantity of data of the test device. The data quantity of the boundary scan datum is effectively compressed, storage space is saved, test time and cost are reduced, and production efficiency is increased.

The invention relates to a three-step sign test method combined with odd-even check. Test steps of the three-step sign test method combined with the odd-even check comprise that step 1, the corresponding boolean expression of a circuit is read from a text; step 2, the boolean expression is analyzed to generate corresponding intermediate data and the odd-even check is conducted; step 3 based on a foundation of the odd-even check, a first step sign test judgment, a second step sign test and a third step sign test judgment are conducted according to the intermediate data correspondingly generated; step 4, a test result is recorded in a textual mode. The three-step sign test method combined with the odd-even check has the advantages of improving test efficiency and a failure coverage rate of the sign test simultaneously and enabling a former circuit not capable of testing a sign to be capable of conducting the sign test. The three-step sign test method combined with the odd-even check brings in the odd-even test based on a traditional sign test in the first place, preprocesses the circuit being tested, improves test efficiency, conducts further sublimation process on the sign test to form the second step sign test and the third step sign test, and improves the failure coverage rate of the test.

The invention relates to the communication field, in particular to an integrated comprehensive drive test instrument. It is used to solve the problem of multiple network competition tests at the same time. The method is: the antenna matching circuit module is used to receive the total downlink signal sent by the same radio frequency antenna, and send each downlink signal after frequency band division to the terminal multi-module group The module is a terminal multi-module module, which is connected to the antenna matching circuit module and includes a first-type module set for receiving a downlink signal on a corresponding frequency band and testing and comparing service-related parameters. In this way, it is ensured that the downlink signals come from the same radio frequency antenna, the evaluation error caused by different radio frequency antennas is reduced, the accuracy of the test comparison of related parameters is improved, and the business correlation of different frequency bands belonging to multiple networks can be simultaneously Test and compare parameters, realize test comparison of various networks, reduce test overhead, simplify operation process, and improve the efficiency of test comparison.