Integrated circuit test system and method

An integrated circuit and test system technology, applied in the direction of measuring electricity, measuring devices, measuring electrical variables, etc., can solve the problems of high cost and low test rate, achieve the effects of reducing test cost, improving test efficiency, and overcoming low efficiency

Active Publication Date: 2017-12-05
FIFTH ELECTRONICS RES INST OF MINIST OF IND & INFORMATION TECH
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0004] Based on this, it is necessary to provide an integrated circuit test system and method for the problems of low test rate and high overhead of existing integrated circuit test system methods

Method used

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  • Integrated circuit test system and method
  • Integrated circuit test system and method

Examples

Experimental program
Comparison scheme
Effect test

Embodiment 1

[0032] image 3 It is a schematic block diagram of the structure of the integrated circuit testing system in Embodiment 1 of the present invention.

[0033] Such as image 3 As shown, the chip under test refers to the integrated circuit chip to be tested. In the present invention, it is the object under test, and its power supply noise signal needs to be measured. The integrated circuit test system of the present invention comprises a chip to be tested, an automatic test unit and a test interface unit, the chip to be tested and the automatic test unit are connected through the test interface unit, in order to achieve the purpose of the present invention, in the chip to be tested, in addition In addition to the original circuit to realize the original function of the chip, an on-chip test unit needs to be embedded on the chip. The on-chip test unit includes: sample and hold module, calibration module and channel selection module.

[0034] In order to improve test efficiency a...

Embodiment 2

[0041] Figure 4 It is a schematic block diagram of the structure of the integrated circuit testing system in Embodiment 2 of the present invention.

[0042] Such as Figure 4 As shown, the test system includes a chip to be tested, an on-chip test unit, a test interface board and an integrated circuit automatic test equipment (ATE).

[0043] In Embodiment 2, the test interface unit can be a test interface board, and the chip to be tested is installed on the test interface board through a test socket, including a ball grid array package (BGA) package socket, a quad flat package (QFP) package socket, etc. The test interface board provides Vddd, Vssd, Vdda, Vssa, Vbias and other signals for the chip under test ( Figure 5 And the corresponding text description below will give a detailed explanation of the signals represented by these letters) supply voltage, and forward the Vcal, channel control signal, test vector and other signals output by the automatic test unit to the chip u...

Embodiment 1 and 2

[0054] Utilize embodiment 1 and 2 and other embodiments of the present invention:

[0055] (1) It can realize the test of high-speed chips

[0056] Since the present invention applies test vectors to the chip to be tested by an automatic test unit such as ATE, checks the correctness of the output response signal of the chip to be tested, and uses the on-chip test unit to complete the sampling and holding of the bypass signal, and utilizes the internal analog-to-digital conversion of the ATE Module to complete the digitization of the bypass signal, so it can realize the test of the high-speed (such as GHz) chip under test, thereby improving the test efficiency and reducing the test cost;

[0057] (2) It can be integrated with the existing integrated circuit test process

[0058] Existing integrated circuit testing processes are all carried out using ATE, and the embodiment of the present invention does not need to carry out additional technical transformation on ATE, and only ...

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Abstract

The invention relates to an integrated circuit testing system, which includes an automatic testing unit, a testing interface unit, and an on-chip testing unit embedded on a chip to be tested. The on-chip testing unit includes a channel selection module, a sampling and holding module, and a calibration module. The above-mentioned test interface unit is connected with the automatic test unit, and the automatic test unit generates test vectors and path control signals and transmits them to the test interface unit; the path selection module receives the path control signals transferred by the test interface unit, and based on the path control signals to the sampling The hold module or the calibration module outputs a channel selection signal. The present invention realizes the test to the high-speed (such as GHz) chip to be tested; In addition, only the test interface unit is required to complete the electrical connection between the automatic test unit and the chip to be tested, so as to realize the integration of the chip to be tested and the existing integrated circuit test process, thereby improving Improve test efficiency and reduce test overhead.

Description

technical field [0001] The invention relates to the technical field of integrated circuit testing, in particular to a testing system and method for integrated circuit function and safety. Background technique [0002] In recent years, the security of integrated circuits (ICs) has received attention. Due to cost reasons, most integrated circuit design companies do not have their own manufacturing process lines, and mainly rely on professional chip manufacturing foundries (Foundries) for chip production. This separation of design and production has brought hidden dangers to the security of integrated circuits: during the uncontrolled manufacturing process, chips may be implanted with hardware Trojan horses (HTH). Once the hardware Trojan horse is activated, it will disturb the normal function of the chip and leak the key information that the chip is processing. [0003] At present, the method based on bypass analysis (SCA) is usually used to realize the detection of hardware...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G01R31/3167
Inventor 王力纬何春华侯波恩云飞谢少锋
Owner FIFTH ELECTRONICS RES INST OF MINIST OF IND & INFORMATION TECH
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