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A Three-Order Symptom Test Method Combined with Parity Check

A parity check and symptom technology, applied in the field of computer hardware fault testing, can solve the problems of complex circuit fault testing, complex circuit design, and difficulty in circuit fault detection, so as to reduce resources and time overhead and reduce testing. overhead, the effect of improving fault coverage

Inactive Publication Date: 2015-12-02
SHANGHAI UNIV
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0027] With the development of VLSI, the design of circuits has become more and more complex, and the fault testing of circuits has become more and more complicated. Now some fault diagnosis is facing more and more problems, especially It is the issue of time overhead and storage overhead that plagues most fault testing practitioners
In order to adapt to the development of VLSI in the new era, it is necessary to improve the existing fault testing methods so that there is less time and less resources to test more complex circuits
However, in some commercial circuits, especially military ones, some information has a certain degree of confidentiality, and it is even more difficult to detect faults in the circuit.
[0028] At the same time, due to the completeness of the symptom test, it is difficult to guarantee the fault coverage in response to the rapid development of large-scale integrated circuits at this stage

Method used

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  • A Three-Order Symptom Test Method Combined with Parity Check
  • A Three-Order Symptom Test Method Combined with Parity Check
  • A Three-Order Symptom Test Method Combined with Parity Check

Examples

Experimental program
Comparison scheme
Effect test

Embodiment 1

[0066] In this embodiment, the method of the third-order symptom test combined with parity check is based on Microsoftvisualstudio2008, and is implemented with C++ object-oriented language as the programming language.

[0067] image 3 As shown, the method for the third-order symptom test in combination with the parity check comprises the following steps, and is characterized in that,

[0068] Step 1, read the corresponding Boolean expression of the circuit from the text;

[0069] Step 2, analyze Boolean expressions, generate corresponding intermediate data, and perform parity check;

[0070] Included in said step 2, the Boolean expression for the circuit, replacing the general exhaustive (input 2 n Combination) method, disjunctive, and then get disjunctive normal form (DNF). The parity of the circuit is judged according to the obtained disjunction paradigm.

[0071] Step 3 is based on the parity check, and according to the intermediate data generated accordingly, the firs...

Embodiment 2

[0085] This embodiment is basically the same as Embodiment 1, and the special features are as follows:

[0086] The boolean expression: . First perform a parity check on it to get:

[0087]

[0088] is an odd function, therefore, the circuit can be obtainedN For symptom-testable circuits, use first-order symptom testing for fault detection. In this way, pre-checking the circuit using the parity check can effectively reduce the calculation amount of the test and the test time.

Embodiment 3

[0090] This embodiment is basically the same as Embodiment 1, and the special features are as follows:

[0091] The boolean expression:

[0092] a) According to the definition of parity test, it can be obtained:

[0093]

[0094] It can be obtained that the circuit is an even function, so it is necessary to continue to make a testable judgment on the circuit.

[0095] b) According to the definition of the first-order symptom test, variables can be extracted:

[0096]

[0097] At the same time, you can get:

[0098] Unpredictable for first-order symptoms;

[0099] c) Carry out second-order symptom judgment on the circuit and extract variables:

[0100]

[0101] At the same time, you can get: ,

[0102] The circuit is still untestable.

[0103] d) After the third-order symptom judgment of the circuit, it can be obtained

[0104]

[0105] At the same time, after calculation, we get:

[0106]

[0107] At this time, after using the third-order symptom j...

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Abstract

The invention relates to a three-step sign test method combined with odd-even check. Test steps of the three-step sign test method combined with the odd-even check comprise that step 1, the corresponding boolean expression of a circuit is read from a text; step 2, the boolean expression is analyzed to generate corresponding intermediate data and the odd-even check is conducted; step 3 based on a foundation of the odd-even check, a first step sign test judgment, a second step sign test and a third step sign test judgment are conducted according to the intermediate data correspondingly generated; step 4, a test result is recorded in a textual mode. The three-step sign test method combined with the odd-even check has the advantages of improving test efficiency and a failure coverage rate of the sign test simultaneously and enabling a former circuit not capable of testing a sign to be capable of conducting the sign test. The three-step sign test method combined with the odd-even check brings in the odd-even test based on a traditional sign test in the first place, preprocesses the circuit being tested, improves test efficiency, conducts further sublimation process on the sign test to form the second step sign test and the third step sign test, and improves the failure coverage rate of the test.

Description

technical field [0001] The invention relates to the field of computer hardware fault testing, in particular to the field of fixed fault diagnosis algorithms based on exhaustive testing, and proposes a third-order symptom testing method combined with parity checks. Background technique [0002] Basic knowledge introduction: [0003] Symptom testing, parity checking is a well-known exhaustive testing based fixed fault diagnosis algorithm that has been used for many years. The exhaustive test method needs to test all possible combinations of a circuit, that is, for a circuit with n input variables, it is to combine all 2 n All input combinations are loaded on the circuit, and then the output response is used to determine whether the circuit is normal. One of the advantages of the exhaustive test method is that it can make more reliable test results for any circuit without knowing the specific design of the circuit. The symptom test has inherited this advantage very well. ...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G06F11/10
Inventor 吴悦童纯纯徐拾义
Owner SHANGHAI UNIV
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