Method for testing dispatching of on-chip systematic embedded logical core by multistage order algorithm

A technology of logic core and sorting algorithm, which is applied in the field of test scheduling of embedded logic core in system-on-chip

Inactive Publication Date: 2011-04-13
SHANGHAI UNIV
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However, it must be noted that these two parts are closely related in fact, and the sorting optimization is optim

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  • Method for testing dispatching of on-chip systematic embedded logical core by multistage order algorithm
  • Method for testing dispatching of on-chip systematic embedded logical core by multistage order algorithm
  • Method for testing dispatching of on-chip systematic embedded logical core by multistage order algorithm

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Embodiment Construction

[0044] A preferred embodiment of the present invention is: see figure 1 , the method of applying the multi-level sorting algorithm to the test scheduling of the embedded logic core of the system on chip, which reads in the SoC file, sets the sorting depth and the priority standard, and uses the multi-level sorting algorithm to obtain the optimal logic core test scheduling. The logic core test scheduling results of the logic core, the operation steps are (1) scheduling matrix Z establishment and initialization, (2) scheduling matrix Z row expansion, (3) scheduling matrix Z row contraction, (4) scheduling matrix Z total test bandwidth - total Test time (W-T) two-dimensional scheduling sorting, (5) double traversal of scheduling matrix Z total test bandwidth-adjustment factor (W-α) and (6) report generation; step (1) scheduling matrix Z establishment and initialization are: read SoC file, which conforms to the SoC file format formulated by ITC'02 (International TestConference 200...

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Abstract

The invention relates to a method for testing dispatching of an on-chip systematic embedded logical core by a multistage order algorithm. The operation method comprises the following steps of: establishing and initializing a dispatching matrix Z; line expanding the dispatching matrix Z; line contracting the dispatching matrix X; two-dimensionally dispatching and sequencing the total testing band width to the total testing time (W-T) of the dispatching matrix Z; double-traversing a total testing band width-adjusting factor (W-alpha) of the dispatching matrix Z; and generating a report. The invention is capable of effectively and integrally solving the two independently problems of the test dispatching of the on-chip systematic embedded logical core and the test link chaining in the logical core, thereby effectively reducing the testing time and testing cost of the on-chip system. The method is convenient in operation, and is applicable to various on-chip systems for finishing the measurability design of the logical core by scanning chain.

Description

technical field [0001] The invention relates to a method for scheduling a test of a system-on-chip embedded logic core, in particular to a method for applying a multi-level sorting algorithm to a test and schedule an embedded logic core of a system-on-chip. Background technique [0002] Due to the use of logic core reuse design methods, the design scale and implementation functions of integrated circuits have undergone a sudden change, from the original VLSI (Very Large Scale Integration Circuit) to the current system-on-chip. However, with the increasing design scale, increasing functional complexity and shortening design cycle of SoC, a serious problem is becoming more and more obvious, that is, the testing of SoC has become a bottleneck problem hindering the development of SoC. Effectively reducing the test difficulty and test cost of SoC has become a very important way to improve the comprehensive competitiveness of SoC. [0003] Due to the complexity and diversity of m...

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Application Information

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IPC IPC(8): G01R31/3185
Inventor 张金艺翁寒一李娇蔡万林丁梦玲黄徐辉王春华段苏阳吴玉见
Owner SHANGHAI UNIV
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