Addressing module structure for realizing digital signal processor

A technology of addressing modules and digital signals, which is applied in the direction of electrical digital data processing, instruments, memory systems, etc., can solve the problems of increasing the complexity of address allocation, the address cannot be flexibly supported, and it is not convenient for programmers to use, so as to reduce the instruction overhead , Small circuit delay, the effect of increasing flexibility

Inactive Publication Date: 2011-08-24
SHANGHAI JIAO TONG UNIV +1
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

In addition, the circuit structure also restricts the first address of circular addressing. The length of the circular buffer is recorded as L1, then the lowest k1 bit of the first address of circular addressing must be zero, and k1 satisfies the relation 2 k1 >The smallest natural number of L1
In view of the

Method used

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  • Addressing module structure for realizing digital signal processor
  • Addressing module structure for realizing digital signal processor
  • Addressing module structure for realizing digital signal processor

Examples

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Embodiment Construction

[0034] The embodiments of the present invention are described in detail below. This embodiment is implemented on the premise of the technical solution of the present invention, and detailed implementation methods and specific operating procedures are provided, but the protection scope of the present invention is not limited to the following implementation example.

[0035] Such as image 3 As shown, this embodiment includes: an address calculation unit 1110 and an address register file 1120; wherein:

[0036] The address calculation unit 1110 includes at least one address calculation module 1111, 1112, and outputs one or more addresses used by the digital signal processor for memory access. The address calculation unit 1110 receives the control signal and the current address from the address register file 1120 , and outputs the updated address to the address register file 1120 .

[0037] The addressing register file 1120 includes an addressing register 1121 and a control reg...

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Abstract

The invention discloses an addressing module structure for realizing a digital signal processor in the field of computer system structures. The addressing module structure comprises an address computation unit and an addressing register file which is connected with the address computation unit, wherein the address computation unit outputs an updated address to the addressing register file and receives a current address and a control signal. The addressing module structure can finish computation of the address within a clock period, have extremely-low circuit delay and meet a requirement of a high-performance signal processor on a high-operation speed.

Description

technical field [0001] The invention relates to a device in the technical field of digital signal processing, in particular to an addressing module structure for realizing a digital signal processor. Background technique [0002] In commonly used digital signal processing algorithms, data addressing usually has the following three methods: sequential addressing, circular addressing, and bit-flip addressing. Traditional digital signal processors only support computationally simple sequential addressing, and often fail to achieve high performance when implementing digital signal processing algorithms. In addition, some processors also support circular addressing and bit-flip addressing, but there are more restrictions on addresses. For example, the starting address of the buffer set when performing circular addressing must be a power of 2, or the When addressing, the first address must be a power of 2. These restrictions greatly weaken the flexibility of addressing and creat...

Claims

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Application Information

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IPC IPC(8): G06F9/34
Inventor 卫振琦孔吉刘佩林
Owner SHANGHAI JIAO TONG UNIV
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