Device and method for calibrating capacitor array type successive-approximation analog-to-digital converter

Abstract

The invention relates to a device and method for calibrating a capacitor array type successive-approximation analog-to-digital converter, which belong to the field of mixed-signal integrated circuit design; the device comprises a capacitance measurement circuit, a static memory, a control circuit corresponding to the static memory, and a logical operation unit connected between the capacitance measurement circuit and the static memory; and the method comprises the following steps: measuring the true values of each pair of capacitors in a capacitor array to be calibrated by using the capacitance measurement circuit; according to the actual structure of the capacitor array, calculating the true weight values of each pair of capacitors according to the measured true values by using the logical operation unit, mapping the weight values into n-bit binary weight codes, and storing the binary weight codes into the static memory so as to form a final weight code table; and carrying out corresponding correction on the output codes of the analog-to-digital converter to be calibrated by using the final weight code table so as to obtain the finally-calibrated output codes. The device and method provided by the invention have the advantages in the aspects of hardware cost and conversion rate.

Description

technical field [0001] The invention belongs to the field of mixed-signal integrated circuit design, and particularly relates to a calibrating method of a capacitance array type successive approximation analog-to-digital converter, which can compensate capacitance mismatch caused by process deviation. Background technique [0002] With the development of the information industry, the digital signal processing technology is changing with each passing day, and the analog-to-digital / digital-to-analog (A / D, D / A) converter as a bridge connecting the analog and digital worlds has also been more and more widely used. With the improvement of digital signal processing speed, it will inevitably put forward high-speed and high-precision requirements for analog-to-digital / digital-analog converters; at the same time, the vigorous development of portable consumer electronics and medical equipment also requires analog-to-digital / digital-analog converters. requirements for low power consump...

AI Technical Summary

Problems solved by technology

[0006] At present, the capacitance-to-array successive approximation analog-to-digital converter has the following two shortcomings: 1. The capacitor array is usually in the form of binary weights, so that the total capacitance increases with the conversion accuracy as a power function; 2. The capacitance matching accuracy is limited.

After taking into account the mismatch, image 3 The actual value of each capacitance shown can be expressed as and image 3 The structure shown can double the total capacitance, but each segment is still in the form of binary weight, and the influence of capacitance mismatch still exists; as for the second problem, predecessors have proposed many solutions from the aspects of layout and calibration. Such as adding virtual redundant capacitors on the layout, adopting a common center structure, etc., such as Figure 4 As shown, each small box in the figure represents a unit capacitance, and the same number indicates its parallel connection. For example, all four capacitors marked with 4 are connected in parallel to produce four times the unit capacitance, and the other is the same

These methods can overcome the inherent error caused by the uneven thickness of the dielectric plate due to the process production conditions to a certain extent, but they also bring two problems: 1. The connection is complicated and the parasitic is serious; 2. The number of virtual redundant capacitors is considerable. , the area efficiency is greatly reduced

[0008] This method has two major disadvantages: first, it needs a higher-precision converter to quantize the residual voltage, and usually the residual voltage is relatively small, which adds to the difficulty of quantization; second, it needs to use the successive approximation In the process of correcting the original voltage in real time, there is a hidden danger of affecting the conversion speed. When the stabilization time required for the residual correction is greater than the charge redistribution time, the gap between the two comparisons will have to be extended, thereby reducing the conversion rate.

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