Resetting circuit

Abstract

The invention discloses a resetting circuit for adjusting the potential of the output terminal of a shift buffer, which comprises a driving module and a resetting module of the resetting circuit. The driving module receives inducing signals and provides the inducing signals to the output terminal of the driving module. The resetting module is electrically coupled to the output terminal of the shift buffer and the output terminal of the driving module. The potential of the output terminal of the driving module controls whether the electricity between the output terminal of the shift buffer and a first preset potential is turned on or not by the resetting module.

Description

technical field [0001] The present invention relates to the field of display technology, and in particular to a structure of a reset circuit suitable for adjusting the potential of an output end of a shift register. Background technique [0002] Press, with the development of science and technology, flat panel displays (such as liquid crystal displays) are widely used in mobile phones, notebook computers, desktops, etc. due to their advantages of high image quality, small size, light weight and wide application range. In various consumer electronic products such as display devices and televisions, it has gradually replaced traditional cathode ray tube displays and become the mainstream of displays. [0003] At present, in order to reduce the cost of flat panel displays, Gate-on-Array (GOA) and Half-source Driving (HSD) technologies have been developed. Usually, the gate driving circuit on the array includes a plurality of shift registers connected in series to output a plur...

AI Technical Summary

Problems solved by technology

[0005] However, when the process variation of the transistors T41 and T42 in the pull-down circuit 100 is too large, it will cause the control signal Q(n) to leak to the gate-off signal level VSS earlier in the period t instead of as figure 2 As shown by the dotted line in the period t, the gate drive pulse G(n) cannot be closed normally, which will cause the gate drive pulse G(n) to drag (such as figure 2 The waveform of G(n) in the middle period t), when the dragging is too long, it will lead to wrong filling of pixel data in the screen, resulting in abnormal screen display

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