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Method for producing grid of semiconductor device

A semiconductor and device technology, which is applied in the field of manufacturing semiconductor device gates, can solve the problems of different uniformity of key dimensions and unsatisfactory etching CD deviation range, etc.

Active Publication Date: 2013-06-12
SEMICON MFG INT (SHANGHAI) CORP +1
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0013] Due to the above-mentioned defects in the traditional process of trimming the mask by controlling the trimming time, an improved process method is needed, which can effectively solve the difference in the uniformity of critical dimensions caused by the difference in controlling the trimming time and the difference in the full pitch range on the wafer. The etch CD deviation range does not meet the process requirements, so that the mask trimming process can be performed within a larger process window and the same critical dimension uniformity can be obtained between different wafers

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  • Method for producing grid of semiconductor device
  • Method for producing grid of semiconductor device
  • Method for producing grid of semiconductor device

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Embodiment Construction

[0038] In the following description, numerous specific details are given in order to provide a more thorough understanding of the present invention. It will be apparent, however, to one skilled in the art that the present invention may be practiced without one or more of these details. In other examples, some technical features known in the art are not described in order to avoid confusion with the present invention.

[0039] In order to thoroughly understand the present invention, detailed steps will be presented in the following description to illustrate how the present invention fabricates gates to solve the problems of different critical dimension uniformity between different wafers and a small process window. Obviously, the practice of the invention is not limited to specific details familiar to those skilled in the semiconductor arts. Preferred embodiments of the present invention are described in detail below, however, the present invention may have other embodiments b...

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Abstract

The invention discloses a method for producing a grid of a semiconductor device, comprising the steps of: sequentially forming a grid oxide layer, a grid material layer, a finishing layer, an anti-reflecting coating layer and a photoresist layer with patterns on a front end device layer; etching the anti-reflecting coating layer by using the photoresist layer with the patterns as a mask to exposethe upper surface of the finishing layer; primarily etching the finishing layer by using first etching gas containing oxygen to form an opening with a depth as 10-70% of thickness of the finishing layer; slightly adjusting the size of the opening by using second etching gas containing oxygen, and etching the remainder finishing layer to form a finishing layer with patterns, wherein the slight adjustment is performed by controlling the flow speed of the oxygen in the second etching gas; and sequentially etching the grid material layer and the grid oxide layer by using the finishing layer with the patterns as a mask to form a grid. By using the method disclosed by the invention, the mask finishing technique can be performed in a larger technique window; and the same key size uniformity can be obtained.

Description

technical field [0001] The invention relates to a semiconductor manufacturing process, in particular to a method for manufacturing a gate of a semiconductor device. Background technique [0002] At present, with the development of ultra-large-scale integrated circuits, the circuit design size is getting smaller and smaller, especially in the technology node below 45nm, the change of the critical dimension (CD, Critical Dimension) of the circuit has more and more influence on the performance of the device. Large, such as changes in the critical dimensions of the circuit will directly lead to changes in the operating speed of the device. [0003] Due to the impact of the resolution limit of the exposure machine (optical exposure too1), the optical proximity effect (OPE, Optical Proximity Effect). The optical proximity effect originates from the fact that when the circuit patterns with very close pitches on the mask plate are transferred to the photoresist of the semiconducto...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L21/28H01L21/336H01L27/02
Inventor 孙武张海洋黄怡孟晓莹
Owner SEMICON MFG INT (SHANGHAI) CORP