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Programming method of double split gate flash memory array

A technology of storage array and programming method, which is applied in the field of programming of double-separated gate flash memory array, can solve the problems of affecting the programming effect, mutual interference of storage cells, etc., and achieve the effect of improving the programming quality

Active Publication Date: 2015-08-19
SHANGHAI HUAHONG GRACE SEMICON MFG CORP
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  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0007] However, since the storage unit of the double split gate flash memory includes two storage bits, and there is a bit line sharing in the corresponding storage array, in the programming process, there will be a gap between the storage units sharing the same bit line. Mutual interference, affect the programming effect

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  • Programming method of double split gate flash memory array
  • Programming method of double split gate flash memory array
  • Programming method of double split gate flash memory array

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Embodiment Construction

[0027] In order to make the above objects, features and advantages of the present invention more obvious and comprehensible, specific implementations of the present invention will be described in detail below in conjunction with the accompanying drawings and embodiments.

[0028] In the following description, many specific details are set forth in order to fully understand the present invention, but the present invention can also be implemented in other ways than those described here, so the present invention is not limited by the specific embodiments disclosed below.

[0029] image 3 It is a schematic flowchart of a programming method for a double split gate flash memory array according to an embodiment of the present invention. This method is used to program the first storage bit in a target memory cell in the double split gate flash memory array. The double split-gate flash memory array includes a plurality of memory cells arranged in an array, and each memory cell ...

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Abstract

A programming method for a double split gate flash memory array, comprising: charging the middle electrode of a target memory cell to a word line voltage, and charging the control gate corresponding to the first storage bit of the target memory cell to a control gate programming voltage , charge the other control gates to the control gate preprogramming voltage, which is greater than the control gate preprogramming voltage; charge all bit lines to the bit line preprogramming voltage; the first bit line and the second bit line A current is formed between the lines, the first bit line is connected to the bit line electrode of the first storage bit, and the second bit line is connected to the bit line electrode of another storage bit of the target memory cell, and keeps sharing the bit line electrode The voltage of another bit line connected to the memory cells of the adjacent column of the bit line is the same as the voltage of the second bit line. The invention improves the programming quality of the double split gate flash memory array.

Description

technical field [0001] The invention relates to the field of memory technology, in particular to a programming method for a double split gate flash memory array. Background technique [0002] As a kind of integrated circuit storage device, flash memory (flash memory) has the function of electrically erasable and writable storage information, and the stored information will not be lost after power failure. Therefore, flash memory is widely used such as portable computer , mobile phones, digital music players and other electronic products. Generally, according to different gate structures, flash memory is divided into two types: stacked gate flash memory and split gate flash memory. Arranged, each memory cell is used to store a single bit of data. The storage array of the flash memory needs a field oxide layer or a trench insulating layer to separate the memory cells. At the same time, in order to improve the erasing efficiency of the flash memory, it is necessary to increas...

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G11C16/04G11C16/10
Inventor 杨光军
Owner SHANGHAI HUAHONG GRACE SEMICON MFG CORP