Method for manufacturing semiconductor device structure with P-type polysilicon gate

Abstract

The invention provides a method for manufacturing a semiconductor device structure with a P-type polysilicon gate. Sheet resistance of the P-type polysilicon gate is a target value. The method comprises the following steps of: providing a substrate on which the P-type polysilicon gate is arranged; forming a gasket material layer and a gap wall material layer on the substrate and the P-type polysilicon gate sequentially, wherein the gasket material layer comprises a first oxide deposited at first deposition temperature, the gap wall material layer comprises a second oxide deposited at second deposition temperature, the first deposition temperature and / or the second deposition temperature are / is set according to the target value; removing a part, positioned above the substrate and the P-type polysilicon gate, of the gap wall material layer; and forming a source and a drain in the substrate on two sides of the P-type polysilicon gate through ion injection and annealing. By the method, the sheet resistance of the P-type polysilicon gate can be independently adjusted to the target value.

Description

technical field [0001] The invention relates to a semiconductor manufacturing process, in particular to a method for manufacturing a semiconductor device structure with a P-type polysilicon gate. Background technique [0002] In the fabrication of complex integrated circuits using CMOS technology, millions of transistors (eg, NMOS transistors and PMOS transistors) are formed on a semiconductor substrate. Each transistor contains an input electrode called a gate, which can be made of a doped polysilicon gate. NMOS transistors and PMOS transistors are obtained by doping different types of conductive particles in polysilicon gates. [0003] Figure 1A to Figure 1D It is a cross-sectional view of each step in the process of making a CMOS device structure using a traditional method. [0004] Such as Figure 1A As shown, a substrate 101 is provided having an NMOS region 103 and a PMOS region 104 formed thereon and separated from each other by a shallow trench isolation structur...

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Problems solved by technology

[0013] In order to solve the problem that the sheet resistance of the polysilicon gate cannot be accurately controlled in the prior art, the present invention provides a method for manufacturing a semiconductor device structure with a P-type polysilicon gate, the sheet resistance of the P-type polysilicon gate is a target value, The method includes: providing a substrate with a P-type polysilicon gate on the substrate; sequentially forming a liner material layer and a spacer material layer on the substrate and the P-type polysilicon gate, and the liner material layer comprising a first oxide deposited at a first deposition temperature, the spacer material layer comprising a second oxide deposited at a second deposition temperature; removing the spacer material layer is located between the substrate and the P-type The part above the polysilicon gate; forming a source and a drain in the substrate on both sides of the P-type polysilicon gate by ion implantation and annealing, wherein, according to the target value, setting the first deposition temperature and / or or the second deposition temperature, the setting includes: setting the first deposition temperature or the second deposition temperature as the temperature value corresponding to the target value on the pre-determined first relationship curve, the first The relationship curve is the relationship curve between the sheet resistance of the P-type polysilicon gate on the substrate and the deposition temperature of the first oxide or the second oxide; or the first deposition temperature and the second oxide The two deposition temperatures are both set to the temperature values ​​corresponding to the target value on the pre-determined second relationship curve, the first deposition temperature is the same as the second deposition temperature, and the second relationship curve is the The relationship curve between the sheet resistance of the P-type polysilicon gate on the bottom and the deposition temperature of the first oxide and the second oxide, in the second relationship curve, with respect to the same sheet resistance, The deposition temperature of the first oxide is the same as the deposition temperature of the second oxide

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