Clock multiplying circuit, solid-state imaging device, and phase-shift circuit

Abstract

A clock multiplying circuit includes: first and second inverters being ON / OFF-controlled by a positive- or negative-phase signal, respectively, of a first clock signal and including current source and current sync terminals; a capacitive element provided between output ends of the inverters; a current supplying unit increasing, if a frequency of the first clock signal increases, the control current and supplying the control current to the current source terminals of the inverters and outputting, from the current sync terminals of the inverters, a control current the same current amount as that of a control current to the current source terminal; a differential detecting unit receiving input of a potential difference signal between both electrodes of the capacitive element and generating a second clock signal having a phase difference of 90 degrees; and a multiplied-signal generating unit generating a double signal of the first clock signal on the basis of the first and second clock signals.

Description

technical field [0001] The present invention relates to a circuit for doubling the frequency of a clock signal, a solid-state imaging device including the circuit, and a phase shift circuit for the clock signal. Background technique [0002] In the past, in various electronic devices, clock signals have been used to control the operation of the electronic devices. Examples of control include operation control for a 2:1 parallel-to-serial conversion circuit and the like (for example: see JP-A-2002-9629 (Patent Document 1)). [0003] Figure 4 A schematic configuration of a 2:1 parallel-serial conversion circuit described in Patent Document 1 is shown. Figure 4 The shown 2:1 parallel-serial conversion circuit is used for a circuit such as a USB (Universal Serial Bus) interface that converts parallel data into serial data and outputs the serial data. [0004] The 2:1 parallel-to-serial conversion circuit 100 includes two flip-flop circuits 101 and 102 for retiming, which conv...

AI Technical Summary

Problems solved by technology

However, when the fluctuation of the duty cycle of the reference clock signal is large, the setup / hold margin decreases

As a result, errors may appear in the output data

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