Clamp-like movement delayed circuit with output signal repeat sycle different from input signal

Abstract

A delay circuit has a first delay line propagating an input pulse from stage to stage in one direction, a second delay line propagating the previous input pulse from stage to stage in the opposite direction and a comparator operative compare output potential levels of the stages incorporated in the first delay line with output potential levels of the stages incorporated in the second delay line so as to determine if any pair of output potentials are consistent in logic level with one another; when the output potentials are consistent with one another, an output timing signal is produced, and the pulse repetition period of the output timing signal is exactly half as long as that of the input pulse signal.

Description

technical field

[0001] The present invention relates to a delay circuit, and more particularly, to a clamp motion delay circuit which can generate an output signal having a pulse repetition period different from that of the input signal. Background technique

[0002] In Japanese Laid-Open Patent Application (JPA) No. 8-237091, the present inventor proposed a synchronous delay circuit. Previous synchronous delay circuits produced a timing signal whose repetition period was half that of the clock signal. figure 1 represents a delay circuit previously proposed by the present inventors.

[0003] The delay circuit is composed of a first delay line 1, a second delay line 2 and a transfer circuit 3 connected between the delay lines 1 and 2. The first delay line 1 is realized by one column of delay elements, and the second delay line is formed by two columns of delay elements. The transfer circuit 3 includes parallel transformation gates. Each input node of the conversion gate i...

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