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Clamp-like movement delayed circuit with output signal repeat sycle different from input signal

An input signal, delay circuit technology, applied in the direction of single output arrangement, automatic power control, generation/distribution of signals, etc., can solve the problem of not considering the layout of delay lines, etc.

Inactive Publication Date: 2003-08-13
RENESAS ELECTRONICS CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, even if the delay element is selected as 2:1, the layout of the delay line 1 / 2 is still not considered, and some layouts cannot ensure that the two delays are 2:1

Method used

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  • Clamp-like movement delayed circuit with output signal repeat sycle different from input signal
  • Clamp-like movement delayed circuit with output signal repeat sycle different from input signal
  • Clamp-like movement delayed circuit with output signal repeat sycle different from input signal

Examples

Experimental program
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Embodiment Construction

[0025] specific implementation plan

[0026] see first figure 2 , embodies the delay circuit of the present invention by a first delay line 11 that transmits the input clock signal CLK10 to the right, a second delay line 12 that transmits the clock signal CLK10 to the left, and a second delay line 12 that is connected to the first delay line 11 and the second delay line 12 A transfer circuit 13 for transferring a group of clock signals CLK10 from the first delay line 11 to the second delay line 12, and a transfer circuit 13 connected between the first delay line 11 and the second delay line 12 to generate the output clock signal Comparator 14 of CLK11 constitutes. The transfer circuit 13 is responsive to the next clock signal CLK10 serving as the timing control signal CTL10 , and transfers a set of clock signals CLK10 from the first delay line 11 to the second delay line 12 . The direction in which the second delay line 12 transmits the clock signal CLK10 is opposite to tha...

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PUM

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Abstract

A delay circuit has a first delay line propagating an input pulse from stage to stage in one direction, a second delay line propagating the previous input pulse from stage to stage in the opposite direction and a comparator operative compare output potential levels of the stages incorporated in the first delay line with output potential levels of the stages incorporated in the second delay line so as to determine if any pair of output potentials are consistent in logic level with one another; when the output potentials are consistent with one another, an output timing signal is produced, and the pulse repetition period of the output timing signal is exactly half as long as that of the input pulse signal.

Description

technical field [0001] The present invention relates to a delay circuit, and more particularly, to a clamp motion delay circuit which can generate an output signal having a pulse repetition period different from that of the input signal. Background technique [0002] In Japanese Laid-Open Patent Application (JPA) No. 8-237091, the present inventor proposed a synchronous delay circuit. Previous synchronous delay circuits produced a timing signal whose repetition period was half that of the clock signal. figure 1 represents a delay circuit previously proposed by the present inventors. [0003] The delay circuit is composed of a first delay line 1, a second delay line 2 and a transfer circuit 3 connected between the delay lines 1 and 2. The first delay line 1 is realized by one column of delay elements, and the second delay line is formed by two columns of delay elements. The transfer circuit 3 includes parallel transformation gates. Each input node of the conversion gate i...

Claims

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Application Information

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IPC IPC(8): G06F1/10G11C11/407G11C11/4076H03H11/26H03K5/13H03K5/135H03L7/00
CPCH03K5/132H03K5/133H03K5/135G11C7/22H03K5/14
Inventor 佐伯贵范
Owner RENESAS ELECTRONICS CORP
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