Semiconductor encapsulating structure and manufacturing method thereof

Abstract

The invention discloses a semiconductor encapsulating structure and a manufacturing method thereof. The semiconductor encapsulating structure comprises a dielectric layer, a patterned metal layer, a loading plate, a metal layer and a semiconductor element, wherein the dielectric layer is provided with a first surface, a second surface and an opening; the patterned metal layer is formed on the first surface; the loading plate is arranged on the second surface and provided with a third surface, a fourth surface and at least one through hole; the opening is exposed out of part of the third surface and the through hole; the metal layer is formed on the fourth surface and provided with a containing groove and at least one heat conducting column which is extended from the fourth surface and arranged in the through hole; one end of the heat conducting column is protruded out of the third surface, the containing groove is arranged on the end of the heat conducting column; and the semiconductor element is arranged in the opening and also in the containing groove.

Description

technical field [0001] The present invention relates to a package structure (package structure) and its manufacturing method, and in particular to a package with high heat conduction requirement and its carrier structure and its manufacturing method. Background technique [0002] The purpose of chip packaging is to provide proper signal path, heat conduction path and structural protection of the chip. Traditional wirebonding technology usually uses a leadframe as a chip carrier. As the chip's contact density gradually increases, the lead frame can no longer provide a higher contact density, so it can be replaced by a package substrate with a high contact density, and conduct electricity through metal wires or bumps. Media, the chip is packaged on the packaging substrate. [0003] Generally, an adhesive layer conforming to the chip is usually arranged between the chip and the packaging substrate. The chip is fixed on the packaging substrate through the adhesive layer and i...

AI Technical Summary

Problems solved by technology

When silver epoxy is selected as the material of the adhesive layer, due to the poor thermal conductivity of silver epoxy (less than 20W / mK), high expansion coefficient (greater than 30ppm / K) and poor adhesion strength, the heat generated by the chip passes through When the adhesive layer is transferred to the package substrate, the adhesive layer will increase the thermal resistance, which will lead to poor heat conduction, and the strength of the adhesive layer will be reduced or even destroyed when thermal stress occurs.

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