Electrical property analysis method for liquid crystal panel display driving chip

A liquid crystal panel and display driver technology, applied in the field of failure analysis, can solve problems such as the inability to analyze the electrical properties of the display driver chip of the liquid crystal panel

Inactive Publication Date: 2012-03-21
SHANGHAI FALAB TEST
View PDF4 Cites 0 Cited by
  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0008] In order to solve the problem in the prior art that the soft-failure liquid crystal panel display driver chip cannot be electrically analyzed before and after opening, the present invention proposes the following technical solutions:

Method used

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
View more

Examples

Experimental program
Comparison scheme
Effect test

Embodiment Construction

[0017] The preferred embodiments of the present invention are described in detail below, so that the advantages and features of the present invention can be more easily understood by those skilled in the art, so as to define the protection scope of the present invention more clearly.

[0018] In this embodiment, the effective electrical characteristic analysis is performed on the abnormality of "lack of picture" displayed on a liquid crystal panel of an electronic scale. The specific analysis steps are as follows:

[0019] A. Analyze the display mode of the LCD panel, and find that the LCD panel of the good product displays normally, and the LCD panel of the abnormal product displays the phenomenon of "lack of picture";

[0020] B. After disassembling the LCD panel, conduct research on the circuit board, and determine that the COB packaged LCD driver chip is the main cause of the "lack of picture" abnormality, and study the functions of each pin of the COB packaged chip, and a...

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to view more

PUM

No PUM Login to view more

Abstract

The invention provides an electrical property analysis method for a liquid crystal panel display driving chip, which comprises the following steps: A. analyzing a manifestation mode when the liquid crystal panel display is abnormal, and finding a basis for an energizing mode; B. researching the function of each pin of the liquid crystal panel display driving chip, and determining the pin which needs electrical property judgment; C. according to the pin layout of a chip and the lead layout of a printed circuit board (PCB), determining an electrical property measurement position before uncovering, and measuring the electrical property before uncovering; D. after uncovering, directly probing the pin of the chip by a probe, carrying out energizing measurement, and obtaining the electrical property characteristics after uncovering; and E. comparing the abnormal electrical properties after and before uncovering, and judging whether a failed point is in a packaging level or a wafer level. According to the electrical property analysis method suitable for the liquid crystal panel display driving chip, the electrical properties after and before uncovering can be effectively and reasonably compared, which facilitates subsequently judging whether the failed point is in the packaging level or the wafer level.

Description

[0001] technical field [0002] The invention relates to a failure analysis method, in particular to an electrical property analysis method of a liquid crystal panel display driving chip. [0003] Background technique [0004] In the failure analysis method of the electronics industry, it is generally divided into four levels, which are: wafer-level failure analysis, package-level failure analysis, circuit board-level failure analysis and machine-level failure analysis according to the order of production. In the package-level failure analysis, the traditional package-level failure analysis process can be used to analyze the failure point of the failed device or packaged chip, so as to determine whether the failure is at the package level or at the wafer level. If it is at the wafer level, Subsequent wafer-level failure analysis still needs to be carried out. [0005] In the traditional package-level failure analysis process, if the non-destructive analysis does not find t...

Claims

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to view more

Application Information

Patent Timeline
no application Login to view more
Patent Type & Authority Applications(China)
IPC IPC(8): G09G3/36G01R31/28
Inventor 张涛
Owner SHANGHAI FALAB TEST
Who we serve
  • R&D Engineer
  • R&D Manager
  • IP Professional
Why Eureka
  • Industry Leading Data Capabilities
  • Powerful AI technology
  • Patent DNA Extraction
Social media
Try Eureka
PatSnap group products