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Alignment marks in substrates with through-substrate vias (tsvs)

An alignment mark, a technology in the substrate, applied in the field of devices, can solve the problem of low alignment accuracy on both sides, and achieve the effect of high accuracy

Active Publication Date: 2016-01-20
TAIWAN SEMICON MFG CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0004] Due to the limitations of the IR alignment system, and further due to the thickness variation of the ground silicon substrate, the accuracy of double-sided alignment is low, and the misalignment (axis center difference misalignment) can be as high as about 2μm

Method used

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  • Alignment marks in substrates with through-substrate vias (tsvs)
  • Alignment marks in substrates with through-substrate vias (tsvs)
  • Alignment marks in substrates with through-substrate vias (tsvs)

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Embodiment Construction

[0029] The making and using of preferred embodiments of the invention are discussed in detail below. It should be appreciated, however, that the present invention provides many applicable concepts that can be implemented in a wide variety of specific contexts. The specific embodiments discussed are merely illustrative of specific ways to make and use the invention, and do not limit the scope of the disclosure.

[0030] Novel double-sided alignment marks and methods of forming the same are provided according to embodiments. According to an embodiment an intermediate stage of manufacturing a double sided alignment mark is shown. Variations of the examples are then discussed. Like reference numerals are used to designate like elements in the various figures and illustrated embodiments.

[0031] refer to figure 1 , a wafer 2 comprising a substrate 10 is provided. In one embodiment, substrate 10 is a semiconductor substrate (eg, a bumped silicon substrate, although it may inc...

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PUM

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Abstract

The present invention discloses an apparatus including a substrate and alignment marks including conductive through-substrate vias (TSVs) penetrating the substrate. The invention also discloses a method for forming the device. Through the method and device of the invention, the alignment accuracy of the substrate through holes on the substrate is high.

Description

technical field [0001] The present invention relates to a device, and in particular, the present invention relates to an alignment mark in a substrate having through-substrate holes. Background technique [0002] To form three-dimensional (3D) integrated circuit structures, through-substrate vias (TSVs) are used to electrically connect the front-side features of the wafer to the back-side features. For example, on the front side, there may be interconnect structures and metal bumps. On the back, there may be metal bumps and redistribution lines. In order to align the front part and the back part accurately with each other, double-sided alignment needs to be performed. [0003] Typically, the front side features are formed on the wafer first, and then the silicon substrate in the wafer is thinned by backside grinding until the TSVs are exposed. Incorporates front alignment marks into the front part. To locate the front-side alignment marks, double-sided alignment is perfo...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L23/544H01L23/538H01L21/68H01L21/768
CPCH01L21/6835H01L21/76898H01L23/481H01L23/49827H01L23/544H01L24/03H01L24/05H01L24/11H01L24/13H01L2221/68327H01L2221/6834H01L2221/68381H01L2223/5442H01L2223/54426H01L2224/03002H01L2224/03912H01L2224/0401H01L2224/05166H01L2224/05181H01L2224/05187H01L2224/05647H01L2224/11002H01L2224/1146H01L2224/1147H01L2924/01023H01L2924/01029H01L2924/01033H01L2924/0105H01L2924/01073H01L2924/01074H01L2924/01077H01L2924/01327H01L2924/14H01L2924/04941H01L2924/04953H01L2924/00H01L23/48
Inventor 章鑫蔡方文林俊成邱文智郑心圃
Owner TAIWAN SEMICON MFG CO LTD