Signal event upset resistance D trigger capable of being set and reset

An anti-single-event, trigger technology, applied in the direction of electrical pulse generator circuits, pulse generation, electrical components, etc., can solve the problem of low anti-single-event flipping ability.

Active Publication Date: 2012-03-28
NAT UNIV OF DEFENSE TECH
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0008] The technical problem to be solved by the present invention is to propose a settable and resetable D flip-flop against single event reversal for the current problem that the anti-singl

Method used

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  • Signal event upset resistance D trigger capable of being set and reset
  • Signal event upset resistance D trigger capable of being set and reset
  • Signal event upset resistance D trigger capable of being set and reset

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Embodiment Construction

[0030] figure 1 It is a schematic diagram of the logic structure of a settable and resettable D flip-flop that is resistant to single-event upset in the present invention. The present invention consists of a clock circuit (such as figure 2 shown), reset buffer circuit (such as image 3 shown), the master latch (as Figure 4 shown), slave latches (such as Figure 5 shown) and the output buffer circuit (as Figure 6 shown) composition. The present invention has four inputs and one output. The four input terminals are CK, which is the clock signal input terminal, D, which is the data signal input terminal, SN, which is the set signal input terminal and RN reset signal input terminal; one output terminal is Q, which is the data output signal terminal. The clock circuit receives CK, and outputs C and CN respectively after buffering CK. The reset buffer circuit buffers RN, inputs R which is inverse to RN, and transfers R to the master latch and the slave latch. The main lat...

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PUM

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Abstract

The invention discloses a signal event upset resistance D trigger capable of being set and reset, and is aimed at raising signal event upset resistance capability of the signal event upset resistance D trigger capable of being set and reset. The trigger comprises a clock circuit, a reset buffer circuit, a main latch register, a secondary latch register and an output buffer circuit. The main latch register is composed of 14 PMOS tubes and 14 NMOS tubes. The secondary latch register is composed of 10 PMOS tubes and 10 NMOS tubes. Both the main latch register and the secondary latch register are subjected to duplication redundancy reinforcement, and a C2MOS circuit in the main latch register is improved, i.e., a pull-up PMOS tube and a pull-down tube which are mutually redundant in the C2MOS circuit are separated. The trigger in the invention has strong signal event upset resistance capability, is suitable for a standard cell of a signal event upset resistance reinforcement integrated circuit, and is applied to the fields of aviation, spaceflight and the like.

Description

technical field [0001] The invention relates to a master-slave D flip-flop with a settable and resettable structure, in particular to a settable and resetable D flip-flop against single event upset (signal event upset). Background technique [0002] In cosmic space, there are a large number of high-energy particles (protons, electrons, heavy ions) and charged particles. After the integrated circuit is bombarded by these high-energy particles and charged particles, an electronic pulse will be generated in the integrated circuit, which may cause the original level of the internal node of the integrated circuit to flip. This effect is called single event upset (SEU). The higher the LET (Linear Energy Transfer) value of a single event bombarding an IC, the stronger the resulting electron pulse. Integrated circuits used in aviation and aerospace fields are threatened by single event upsets, which can make integrated circuits work unstable and even cause fatal errors. Therefore, ...

Claims

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Application Information

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IPC IPC(8): H03K3/013H03K3/02
Inventor 梁斌李鹏池雅庆刘必慰刘真李振涛陈建军何益百杜延康
Owner NAT UNIV OF DEFENSE TECH
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