Signal event upset resistance D trigger capable of being set and reset
An anti-single-event, trigger technology, applied in the direction of electrical pulse generator circuits, pulse generation, electrical components, etc., can solve the problem of low anti-single-event flipping ability.
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[0030] figure 1 It is a schematic diagram of the logic structure of a settable and resettable D flip-flop that is resistant to single-event upset in the present invention. The present invention consists of a clock circuit (such as figure 2 shown), reset buffer circuit (such as image 3 shown), the master latch (as Figure 4 shown), slave latches (such as Figure 5 shown) and the output buffer circuit (as Figure 6 shown) composition. The present invention has four inputs and one output. The four input terminals are CK, which is the clock signal input terminal, D, which is the data signal input terminal, SN, which is the set signal input terminal and RN reset signal input terminal; one output terminal is Q, which is the data output signal terminal. The clock circuit receives CK, and outputs C and CN respectively after buffering CK. The reset buffer circuit buffers RN, inputs R which is inverse to RN, and transfers R to the master latch and the slave latch. The main lat...
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