Data error check method, data transfer method, and semiconductor memory

Abstract

Various embodiments of a memory system are disclosed. In one exemplary embodiment, the memory system may include a semiconductor memory apparatus configured to generate error check signals in a column direction and a row direction of data groups to be transmitted through a plurality of data input / output terminals in a read operation and output the error check signals together with the data groups, and a memory controller configured to control data read / write operations of the semiconductor memory apparatus, generate error check signals by performing error check in a column direction and a row direction of data groups to be transmitted in a write operation, and provide the error check signals to the semiconductor memory apparatus together with the data groups.

Description

[0001] Cross References to Related Applications [0002] This application claims priority from Korean Patent Application No. 10-2010-0106861 filed with the Korean Intellectual Property Office on Oct. 29, 2010, the entire contents of which are incorporated herein by reference. technical field [0003] The present invention relates generally to data error checking, and more particularly to a data error checking circuit, a data error checking method, a data transmission method using a data error checking function, a semiconductor memory device and a storage system using a data error checking function. Background technique [0004] A typical semiconductor circuit may have an error check function for checking whether an error has occurred in data in order to improve data reliability of high-speed data transmission. A typical error checking method is a cyclic redundancy check (CRC, cyclic redundancy check) function. [0005] figure 1 is a diagram of a typical semiconductor circu...

AI Technical Summary

Problems solved by technology

[0008] To configure this CRC logic, a total of 328 2-input XOR gates and 42 polynomial equations are required, resulting in an increase in circuit area

[0009] In addition, the final CRC value is calculated by passing through the six-level XOR gate path, resulting in a six-level gate delay

[0010] One problem with typical semiconductor circuits according to the prior art is that the circuit area and error checking time increase due to the equations required by the CRC logic

Images