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Method and system for testing performance of heterojunction bipolar transistor

A technology of heterojunction bipolar and testing methods, applied in the field of heterojunction bipolar transistor performance testing and heterojunction bipolar transistor performance testing system, can solve the problem of inability to quantify and quantify heterojunction bipolar transistors, unclear I-V curve and other issues to achieve the effect of accurate and objective device performance

Active Publication Date: 2013-12-18
SHANGHAI HUAHONG GRACE SEMICON MFG CORP
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Problems solved by technology

[0002] At present, there is no method that can directly or indirectly quantify the trap center (trap center) near the BE junction of a heterojunction bipolar transistor (HBT); although the device can be tested, such as adding Stress, it can be judged according to the shift of the device characteristics (I-V curve) The stability of the device, but it is still unclear what factors caused the shift of the I-V curve, let alone quantify the phenomenon

Method used

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  • Method and system for testing performance of heterojunction bipolar transistor
  • Method and system for testing performance of heterojunction bipolar transistor
  • Method and system for testing performance of heterojunction bipolar transistor

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Embodiment Construction

[0032] The invention discloses a method for testing the performance of a heterojunction bipolar transistor, comprising the following steps:

[0033] Conduct low-frequency noise power spectrum tests on the BE junction of heterojunction bipolar transistor devices, and screen out the spectrum with generation-composite noise characteristics;

[0034] According to the function , to fit the noise part of the screened generation-composite noise characteristic spectrum, in the formula is the capture-release time of the trap center, , is the frequency of the trap center, J B is the current density, the value range of a and k is 1.9~2.1, and C is the fitting constant;

[0035] Find the position of the first inflection point on the fitted curve from the spectrum, and the abscissa value of its position is The value of , the ordinate value is value, independent variable The value is 1, and the value of C is calculated;

[0036] According to the value of C, fit other inflecti...

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Abstract

The invention discloses a method and a system for testing the performance of a heterojunction bipolar transistor, wherein a low-frequency noise testing method is used to analyze a composite noise feature generated in a noise power spectrum of the heterojunction bipolar transistor, a trap center near a BE (Base-Emitter) junction of the heterojunction bipolar transistor is quantized by using a model fit method, and the role of guiding device characteristic analysis and process improvement can be played.

Description

technical field [0001] The invention relates to a testing method of a semiconductor device, in particular to a performance testing method of a heterojunction bipolar transistor. The invention also relates to a performance testing system of the heterojunction bipolar transistor. Background technique [0002] At present, there is no method that can directly or indirectly quantify the trap center (trap center) near the BE junction of a heterojunction bipolar transistor (HBT); although the device can be tested, such as adding Stress, it can be judged according to the shift of the device characteristics (I-V curve) The degree of stability of the device, but it is still unclear what factors cause the shift of the I-V curve, let alone quantify the phenomenon. Contents of the invention [0003] The technical problem to be solved by the present invention is to provide a performance testing method for heterojunction bipolar transistors and a testing system used to realize the perfo...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G01R31/26
Inventor 黄景丰
Owner SHANGHAI HUAHONG GRACE SEMICON MFG CORP
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