Method for designing System on a Chip (SOC) chips with low power consumption for wireless local area network

A technology of wireless local area network and design method, which is applied in the direction of wireless communication, network topology, energy consumption reduction, etc., and can solve problems such as application obstacles, large chip work and standby power consumption, and complexity

Inactive Publication Date: 2012-07-11
BEIJING CEC HUADA ELECTRONIC DESIGN CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, due to the complexity of the algorithm of the communication technology and the SOC implementation system, the chip usually has a large working and standby power consumption, which undoubtedly brings huge obstacles to its application in consumer electronics products, especially handheld electronic products.

Method used

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  • Method for designing System on a Chip (SOC) chips with low power consumption for wireless local area network
  • Method for designing System on a Chip (SOC) chips with low power consumption for wireless local area network
  • Method for designing System on a Chip (SOC) chips with low power consumption for wireless local area network

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Experimental program
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Embodiment Construction

[0014] Introduction to each functional module of the chip

[0015] The module Power Management Unit (referred to as PMU) is powered by an off-chip normally-on 1.2V power supply, and the input clock is an optional low-frequency clock domain of 32.768KHz to 2MHz. The module implements the working state machine of the chip. In addition, during the switching process of each working state of the chip, the PMU module is responsible for completing the power switch and clock gating switch signals of all other circuits of the chip except the PMU circuit;

[0016] The module Host Interface is the protocol processor of the device interface, and the chip performs data interaction with the off-chip master device through the device interface;

[0017] The module Clock Gating Control (CGC) completes the clock gating of each clock domain in the chip Host Interface and BB Subsystem, and completes the clock frequency switching of the Processor module.

[0018] The module Processor is an on-chi...

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Abstract

The invention discloses a method for designing System on a Chip (SOC) chips with low power consumption for a wireless local area network. The method is invented based on the operating mode and characteristics of the SOC chip for the wireless local area network. The method not only reduces dynamic power consumption of the chip, but also further reduces static power consumption of the chip, thereby solving the pressure of ever-increasing static power consumption of chips in a deep sub-micron process.

Description

technical field [0001] The invention relates to a low power consumption design method of a wireless local area network SOC chip in the field of wireless local area network. Background technique [0002] In today's consumer SOC chip design, working and standby power consumption is gradually becoming the measure of successful chips, and the system's standby time is gradually becoming one of the decisive factors related to the success or failure of products. [0003] As a high-speed wireless communication network technology, WLAN technology has not only become the best choice for home wireless routing and PC wireless access, but also has been increasingly widely used in consumer electronics in recent years. However, due to the complexity of the algorithm of the communication technology and the SOC implementation system, the chip usually has a large working and standby power consumption, which undoubtedly brings huge obstacles to its application in consumer electronics products,...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H04W84/12H04W88/02
CPCY02B60/50Y02D30/70
Inventor 周卓刘鹏赵彦光
Owner BEIJING CEC HUADA ELECTRONIC DESIGN CO LTD
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