Semiconductor device with embedded low-k metallization

Abstract

Generally, the subject matter disclosed herein relates to a semiconductor device with embedded low-k metallization. A method is disclosed that includes forming a plurality of copper metallization layers that are coupled to a plurality of logic devices in a logic area of a semiconductor device and, after forming the plurality of copper metallization layers, forming a plurality of capacitors in a memory array of the semiconductor device. The capacitors are formed using a non-low-k dielectric material (k value greater than 3), while the copper metallization layers are formed in layers of low-k dielectric material (k value less than 3). A semiconductor device is also disclosed which includes a plurality of logic devices, a memory array comprising a plurality of capacitors, a conductive contact plate coupled to the plurality of capacitors, and a plurality of copper metallization layers coupled to the logic devices, wherein the plurality of copper metallization layers are positioned at a level that is below a level of a bottom surface of the contact plate. A material other than a low-k dielectric material is positioned between the plurality of capacitors in the memory array.

Description

technical field [0001] The present invention relates generally to complex integrated circuits, and more particularly to semiconductor devices with embedded low-k metallization. Background technique [0002] In modern ultra-high density integrated circuits, the dimensions of device features have been steadily reduced to enhance the performance of the semiconductor devices and the overall functionality of the circuits. However, in response to the continued shrinking of feature sizes, certain size-related issues have surfaced that can at least partially negate the benefits that can be achieved through simple size reduction alone. In general, for example, circuit components such as MOS transistors and the like can result in superior performance characteristics due to the reduced channel length of the transistor components, resulting in higher drive current capability and enhanced switching speed. However, as the channel length is reduced, the spacing between adjacent transisto...

AI Technical Summary

Problems solved by technology

First, the use of non-copper extended length contacts 114 can reduce the operating efficiency of the device 100 compared to how the device 100 would operate if copper were used for the extended length contacts 114

Furthermore, the use of higher-k dielectric materials in the layer 112 (which tends to help as it relates to the performance of the capacitor 110) tends to hurt the signal-to-noise ratio of the device 110

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