Rapid arbiter implementation method and device thereof

Abstract

The invention discloses a rapid arbiter implementation method and a device of the rapid arbiter. The device belongs to the fields of computer interface buses, embedded equipment and automatic control, is mainly applicable to occasions with high speed and multiple equipment, and can be used for completing each poll in a shortest period. An rapid and efficient arbiter is implemented by virtue of the complement-on-two method. As a huge state machine is eliminated, the device is simple in structure and easy to use, and the quantity of input equipment can be flexibly increased and reduced by changing parameters. Therefore, the rapid arbiter implementation device can be effectively applied to interface systems for accessing public resources of a large number of high-speed main equipment.

Description

technical field [0001] The invention is related to the fields of computer interface bus, embedded equipment and automatic control. In a multi-master system, an arbitration grant signal must be provided to each master. The arbiter acts as the generator of the arbitration grant signal in the multi-master system, and generates the grant signal according to the priority. Background technique [0002] In many systems, there is a phenomenon that a large number of master devices access a common resource. A common resource can be a shared memory, a network switch, a specific state machine, or a complex computing element. The arbiter needs to decide how resources are shared among multiple masters. When an arbiter is put into a design, many factors need to be considered. The interface between the master and the arbiter needs to be of appropriate size and speed. [0003] The arbiter of the traditional method is implemented in the form of a state machine. Only one master device has...

AI Technical Summary

Problems solved by technology

The efficiency of the system is very low, and it cannot be used in the occasion of high-speed multi-master equipment