Control circuit of read amplifier of dynamic random access memory (DRAM) and DRAM comprising same

Abstract

The invention belongs to the technical field of a dynamic random access memory (DRAM) and in particular to a control circuit of a read amplifier of the dynamic random access memory (DRAM) and the DRAM comprising the same. The control circuit of the read amplifier comprises a control signal generating circuit, a redundancy unit corresponding to a memory unit of the DRAM and a redundancy word line driving module. Word line delay of the redundancy unit is matched with the word line delay of the memory unit. The DRAM comprises a memory array and a read access of the memory unit in the memory array. The memory array further comprises the redundancy unit. The DRAM further comprises the control circuit of the read amplifier. Read operation of the DRAM is greatly quickened.

Description

technical field [0001] The invention belongs to the technical field of DRAM, and in particular relates to a control circuit of a sense amplifier of the DRAM, in particular to a control circuit of the sense amplifier including redundant units, and a DRAM including the control circuit. Background technique [0002] DRAM (Dynamic Random Access Memory) has been widely used in electronic products such as computers, and its technology development cycle is long and relatively mature. However, since DRAM is a memory that stores information based on charge, its read operation is relatively slow. As the requirements for the speed of the DRAM are getting higher and higher, the current main method is to increase the reading speed by continuously scaling down the DRAM. [0003] Generally, a DRAM includes a storage array and peripheral circuits (for controlling operations such as reading, writing, and refreshing). The storage array is also composed of multiple storage cells arranged in r...

AI Technical Summary

Problems solved by technology

Therefore, this wait will slow down the read operation

[0007] In the second aspect, in general, in DRAM, the process feature size in the memory array is smaller than the process feature size of the peripheral circuit, and, inevitably, there are process fluctuations in the DRAM manufacturing process, and this phenomenon is also As technology advances, process feature sizes continue to scale down as apparent

Therefore, process fluctuations under various process types will cause the delay t1 of the delay module to be difficult to track the delay t of the bit line of the memory cell 位 , thus, adjust t1 by adjusting the number of inverter stages, and then accurately match the bit line delay t of the memory cell 位 is difficult to achieve

In the existing technology, the delay t1 of the delay module in the worst case has to be used (that is, the longest t1 is selected) to provide the control signal SA_ctrl, which will also reduce the speed of the DRAM read operation

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