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An electric fuse storage unit and an electric fuse storage array

A technology of memory cells and memory arrays, applied in the field of semiconductors, to achieve the effect of improving the speed of read operations

Active Publication Date: 2020-06-02
SEMICON MFG INT (SHANGHAI) CORP +1
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

The existence of the above problems makes eFuse technology only be used in applications with a limited number of read operations. For example, when the system is turned on, the corresponding SRAM is used to store the macro data of eFuse, and the number of charging times of the system is less than the number of read operations. , prone to the requirement of matching the SRAM to the system clock speed

Method used

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  • An electric fuse storage unit and an electric fuse storage array
  • An electric fuse storage unit and an electric fuse storage array
  • An electric fuse storage unit and an electric fuse storage array

Examples

Experimental program
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Embodiment 1

[0048] Below, refer to figure 2 An eFuse storage unit proposed by an embodiment of the present invention will be described.

[0049] Exemplarily, as figure 2 The shown eFuse storage unit of the present invention comprises the following elements:

[0050] An electric fuse 20 is included, and the electric fuse 20 has a first end 1 and a second end 2 opposite to the first end 1 . The first end of the electric fuse is connected to a second bit line (not shown).

[0051] Exemplarily, the material of the electric fuse 20 may include polysilicon. Wherein the first end 1 is the anode of the electric fuse 20 , and the second end is the cathode of the electric fuse 20 .

[0052] It also includes a first transistor 21, the drain of the first transistor 21 is connected to the first terminal 1 of the electric fuse 20, the gate of the first transistor 21 is connected to the read word line RWL, and the first A source of a transistor 21 is connected to the read bit line RBL.

[0053] ...

Embodiment 2

[0062] Another embodiment of the present invention further provides an electric fuse storage array, which includes the electric fuse storage unit in the foregoing embodiments.

[0063] Specifically, refer to image 3 The electric fuse memory array in the embodiment of the present invention is described in detail.

[0064] The electric fuse storage array of this embodiment includes several electric fuse memory cells 30, and the several electric fuse memory cells 30 are arranged in multiple rows and multiple columns, for example, arranged in m rows and n columns, wherein m and n is an integer.

[0065] The electric fuse memory array in the embodiment of the present invention also includes several rows of read bit lines RBL (for example, read bit line RBL1, read bit line RBL2, etc.), several rows of read word lines RWL (for example, read word line RWL1, read word line line RWL2, etc.), several rows of burnt word lines BWL (for example, burnt word line BWL1, burnt word line BWL2...

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Abstract

The present invention provides an electric fuse memory unit and an electric fuse memory array, and relates to the technical field of semiconductors. The electric fuse memory unit comprises: an electric fuse provided with a first terminal and a second terminal opposite to the first terminal; a first transistor, wherein the drain electrode of the first transistor is connected to the first terminal of the electric fuse, the grid electrode of the first transistor is connected to a read word line, and the source electrode of the first transistor is connected to a first bit line; and a second transistor, wherein the drain electrode of the second transistor is connected to the second terminal of the electric fuse, and the grid electrode of the second transistor is connected to a fusing word line. According to the embodiments of the present invention, the NMOS transistor transmission gate connected to the read word line is additionally arranged to overcome the limitation on the read operation, the read and the write are separated by using different NMOS transistors, the flowing read current is limited, the number of the read operations is not limited, and the read operation speed of the electric fuse memory unit can be improved by using the pre-charging circuit and the new read time sequence.

Description

technical field [0001] The invention relates to the technical field of semiconductors, in particular to an electric fuse storage unit and an electric fuse storage array. Background technique [0002] In the field of semiconductor technology, the electronically programmable fuse (eFuse) technology is widely used as a one-time programmable (OTP) memory in many circuits due to its compatibility with CMOS logic devices and ease of use. [0003] According to the theory of electromigration, eFuse technology stores information by whether the electric fuse is blown by the current. The resistance of the polysilicon electric fuse is very small before it is blown, and the resistance can be regarded as infinite after continuous high-current blown, and the electric fuse is broken. status will be maintained permanently. eFuse technology has been widely used in redundant circuits to improve the problem of chip failure or the ID of the chip, the basic code of the device, etc., to replace t...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G11C17/16
Inventor 杨家奇
Owner SEMICON MFG INT (SHANGHAI) CORP
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