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Decoding device

A decoding device and iterative decoding technology, applied in the direction of encoding, code conversion, encoding components, etc., can solve the problems of high hardware implementation complexity and multiple storage resources of a layered decoder, and achieve reduction of hardware implementation complexity, The effect of reducing storage resources

Active Publication Date: 2014-07-16
HUAWEI TECH CO LTD +1
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Problems solved by technology

However, this layered decoder needs two sets of storage units to store the information that the check node transmits to the variable node and the information that the variable node transmits to the check node, which are calculated during the iterative decoding process of the LDPC code, respectively. , the layered decoder needs more storage resources, resulting in high complexity of the hardware implementation of the layered decoder

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Embodiment 1

[0023] QC-LDPC code is a subclass of LDPC code, and its check matrix H matrix can be composed of multiple sub-matrices belonging to the cyclic permutation matrix, wherein the cyclic permutation matrix is ​​a matrix obtained by cyclically shifting the identity matrix to the right.

[0024] In the first embodiment of the present invention, it is assumed that the check matrix H of the QC-LDPC code is composed of J×L sub-matrices belonging to the cyclic permutation matrix, and each sub-matrix has a size of z×z, then the QC-LDPC code has J× z check nodes and L×z variable nodes. The J×z check nodes of the QC-LDPC code are divided into J layers of check nodes, and each layer of check nodes includes z check nodes. Each layer of check nodes is further divided into G groups, and each group of check nodes includes z / G check nodes.

[0025] In Embodiment 1 of the present invention, N MAX iterations, and in each iterative decoding process of the QC-LDPC code, the QC-LDPC code is processe...

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Abstract

The invention relates a decoding device. The decoding device comprises a storage module that is used for storing channel information of various variable nodes in bipartite graph of low-density parity-check QC-LDPC codes and external information transmitted between various check nodes and various variable nodes of the QC-LDPC codes in the process of iterative decoding for the QC-LDPC, wherein the external information transmitted between any two conjoint check node C and variable node V of the QC-LDPC codes store on the same storage position of the storage module; an updating module that is used for computing the external information transmitted between various check nodes and various variable nodes of the QC-LDPC codes and writing the computed external information in the storing module to update the external information stored in the storage module by the way of dividing various check nodes of the QC-LDPC codes into multi-layer check nodes and layer-to-layer processing according to the channel information and the external information stored on the storage module in the process of each iterative decoding of the QC-LDPC codes, and is used for computing posterior probability information of various variable nodes of the QC-LDPC codes according to the channel information and the external information stored on the storage module and the computed external information; and a computing module that is used for computing decision value of various code bit of the QC-LDPC codes according to the computed posterior probability information of various variable nodes of the QC-LDPC codes. The decoding device can decrease the required storing resource and can reduce hardware implement complexity of the decoding device.

Description

technical field [0001] The invention relates to the communication field, in particular to a decoding device for decoding low density parity check codes. Background technique [0002] Low Density Parity Check (LDPC) code is a linear block code, its performance is close to the limit of Shannon channel capacity, therefore, LDPC code has been widely used in wireless communication, satellite communication and other communication fields. [0003] LDPC codes are usually represented by a sparse parity check matrix H. Figure 1A An example of the parity check matrix H is shown. Assuming that the check matrix H of the LDPC code is a matrix of M rows×N columns, the LDPC code can also be used to represent a bipartite graph with M check nodes and N variable nodes, where each check node represents the check matrix One row element of check matrix H, each variable node represents one column element of check matrix H. Figure 1B shows the Figure 1A The bipartite graph of the parity check ...

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H03M13/11
CPCH03M13/114H03M13/116H03M13/1137
Inventor 岑超荣陈旭谭伟文赵越刘重明喻凡
Owner HUAWEI TECH CO LTD
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