Video processing on-chip system of double AHB (Advanced High Performance Bus) buses

Abstract

The invention discloses a video processing on-chip system of double AHBs (advanced high performance buses), which improves the system reliability and the data transmission speed. The video processing on-chip system comprises two sets of AHBs which are used as inner high-speed data channels, and one set of AHB; one set of AHB is connected with a processor, a common internal memory controller, an Ethernet MAC, a debugging supporting unit and a video coder-decoder; the common internal memory controller is connected with an external storage and the external storage is used as an internal memory for operating the processor and is also used as a display buffer memory of an OSD (on-screen display) image and the video coder-decoder; the other AHB is connected with a video input processing unit, a video debugging unit and an SDRAM (synchronous dynamic random access memory) controller; the SDRAM controller is connected with an external SDRAM; the SDRAM is used as a display buffer memory of a video input channel and a PIP (picture-in-picture) video; an APB (advanced peripheral bus) is connected to the AHB through an AHB / APB bridge; the APB is connected to a slow-speed IO (input / output) equipment controller and an access module register; and a video output processing unit is connected between the two sets of the AHBs, and the video output processing unit utilizes a direct internal memory accessing manner to read data of the two sets of the AHBs.

Description

technical field [0001] The invention relates to a video processing system on chip, in particular to a video processing system on chip with dual AHB buses which improves system reliability and data transmission rate. Background technique [0002] The AHB bus is an industrial bus standard developed by ARM, mainly used for the connection between high-performance modules in the system on chip. It includes the following features: single clock edge operation; non-tri-state implementation; support burst transmission; support split Segment transmission; support multiple master controllers; configurable bus width from 32 bits to 128 bits; support byte, nibble and word transmission. The AHB system consists of three parts: the main module, the slave module, and the infrastructure. The transmission on the entire AHB bus is sent by the master module, and the slave module is responsible for the response. The infrastructure is composed of the arbiter, the master module, and the It is comp...

AI Technical Summary

Problems solved by technology

The traditional video processing SoC system adopts a single set of bus. The processor, DSP, and storage interface are all directly connected to the bus. Due to the exclusiveness of the bus operation, when one master device occupies the bus for operation, other master devices Can only wait, this mode of operation makes the efficiency of the system low; in another improved strategy, a dual-bus system is used and connected through a bus bridge, and the two sets of buses in the same bus are independent and can work in parallel , but when operating across the bus, if the master device on bus 1 accesses the slave device on bus 2, then bus 2 is also monopolized and cannot perform other operations, which will also affect the performance of the system

Images