Delay locked loop and application clock generation method of delay locked loop

Abstract

A delay-locked loop includes a first delay unit, a second delay unit, a third delay unit, a phase detector, and a controller. The first delay unit generates a first delay clock according to a clock and a first delay time. The second delay unit generates a second delay clock according to the first delay clock and a second delay time. The third delay unit generates a third delay clock according to the second delay clock and a third delay time. The phase detector generates a phase detection signal according to the clock and the second delay clock. The controller generates and outputs a phase control signal according to the phase detection signal. The second delay unit and the third delay unit adjust the second delay time and the third delay time respectively according to the phase control signal.

Description

technical field [0001] The invention relates to a delay-locked loop and a method for generating an application clock by the delay-locked loop, in particular to an advanced technology suitable for dynamic random access memory without amplifying the delay of the noise of the dynamic random access memory A phase-locked loop and a method for generating an application clock by a delay-locked loop. Background technique [0002] Please refer to figure 1 , figure 1 It is a schematic diagram illustrating a delay locked loop 100 for the prior art. The DLL 100 includes a first delay unit 102 , a replica delay unit 104 , a phase detector 106 and a controller 108 . Such as figure 1 As shown, the first delay unit 102 generates a delayed clock DCLK according to an input clock XCLK and a first delay time T1 of the first delay unit 102 . The copy delay unit 104 generates a feedback clock FCLK according to the delay clock DCLK and a copy delay time RDT of the copy delay unit 104, wherein...

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Problems solved by technology

like image 3 As shown, because the period of the input clock XCLK is greatly shortened, but the internal delay time IT of the application circuit is not synchronously shortened, in order to make the phase of the output data clock DQ of the application circuit the same as that of the input clock XCLK, although it is still The first delay time T1 can be lengthened so that the rising edge of the feedback clock FCLK is aligned with the rising edge of the next input clock XCLK, but this will cause the total delay in the delay-locked loop 100 to be greater than one of the input clock XCLK. clock cycle, which will cause the noise inside the memory to be amplified

Therefore, the DLL 100 is not suitable for the advanced technology of DRAM

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