A mixed crystal plane strain si strain sige planar bicmos integrated device and its preparation method

A technology of mixed crystal planes and integrated devices, which is applied in semiconductor/solid-state device manufacturing, electric solid-state devices, semiconductor devices, etc., and can solve problems such as low mobility and improved frequency characteristics of BiCMOS integrated circuits

Inactive Publication Date: 2016-03-02
XIDIAN UNIV
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  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0009] The purpose of the present invention is to provide a mixed crystal plane strained Si, strained SiGe planar BiCMOS integrated device and its preparation method, aiming to solve the problem of restricting the improvement of the frequency characteristics of BiCMOS integrated circuits due to the low mobility of Si material carriers

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  • A mixed crystal plane strain si strain sige planar bicmos integrated device and its preparation method

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Embodiment 1

[0100] Embodiment 1: Preparation of 22nm mixed crystal plane strained Si, strained SiGe planar BiCMOS integrated device and circuit, the specific steps are as follows:

[0101] Step 1, SOI substrate material preparation.

[0102] (1a) Select the N-type doping concentration as 1×10 15 cm -3 The Si wafer with a crystal plane of (110) is oxidized on the surface, and the thickness of the oxide layer is 0.5 μm, which is used as the base material of the upper layer, and hydrogen is injected into the base material;

[0103] (1b) Select the P-type doping concentration as 1×10 15 cm -3 The Si sheet with a crystal plane of (100) is oxidized on the surface, and the thickness of the oxide layer is 0.5 μm, which is used as the base material of the lower layer;

[0104] (1c) Using a chemical mechanical polishing (CMP) process to polish the surface of the lower layer and the upper layer of substrate material after hydrogen injection;

[0105] (1d) SiO on the surface of the lower and upp...

Embodiment 2

[0149] Embodiment 2: Preparation of 30nm mixed crystal plane strained Si, strained SiGe planar BiCMOS integrated device and circuit, the specific steps are as follows:

[0150] Step 1, SOI substrate material preparation.

[0151] (1a) Select the N-type doping concentration as 3×10 15 cm -3 The Si wafer with a crystal plane of (110) is oxidized on the surface, and the thickness of the oxide layer is 0.75 μm, which is used as the base material of the upper layer, and hydrogen is injected into the base material;

[0152] (1b) Select the P-type doping concentration as 3×10 15 cm -3 The Si sheet with a crystal plane of (100) is oxidized on the surface, and the thickness of the oxide layer is 0.75 μm, which is used as the base material of the lower layer;

[0153] (1c) Using a chemical mechanical polishing (CMP) process to polish the surface of the substrate material of the lower layer and the upper layer of the active layer after injecting hydrogen, respectively;

[0154] (1d)...

Embodiment 3

[0198] Embodiment 3: Preparation of 45nm mixed crystal plane strained Si, strained SiGe planar BiCMOS integrated device and circuit, the specific steps are as follows:

[0199] Step 1, SOI substrate material preparation.

[0200] (1a) Select the N-type doping concentration as 5×10 15 cm -3 The Si sheet with a crystal plane of (110) is oxidized on the surface, and the thickness of the oxide layer is 1 μm, which is used as the base material of the upper layer, and hydrogen is injected into the base material;

[0201] (1b) Select the P-type doping concentration as 5×10 15 cm -3 The Si wafer with a crystal plane of (100) is oxidized on the surface, and the thickness of the oxide layer is 1 μm, which is used as the base material of the lower layer;

[0202] (1c) Using a chemical mechanical polishing (CMP) process to polish the lower layer and the surface of the upper substrate material after hydrogen injection;

[0203] (1d) SiO on the surface of the lower and upper substrate ...

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Abstract

The invention discloses a mixed crystal face strain Si, strain SiGe and planar BiCMOS (complementary metal oxide semiconductor) integrated device and a preparation method thereof. The method includes steps: preparing an SOI (silicon-on-insulator) substrate, wherein upper basis materials form a crystal face (110), and the lower basis materials form a crystal face (100); preparing deep grooves for isolation on the substrate, etching deep grooves in an active region of a bipolar device, growing N-type Si epitaxy and making a conventional Si bipolar transistor; etching deep grooves in an NMOS device region, selectively growing a strain Si epitaxial layer with the crystal face (100), and preparing a strain Si grooved NMOS device on the strain Si epitaxial layer; and selectively growing a strain SiGe epitaxial layer with the crystal face (110) in an active region of a PMOS device, and preparing a PMOS device and the like on the strain SiGe epitaxial layer. The performance-enhanced mixed crystal face strain Si, strain SiGe and planar BiCMOS integrated device and circuits are prepared by taking the advantages that electron mobility of tension strain Si materials is higher than that of body Si materials and the hole mobility of pressure strain SiGe materials is higher than that of the body Si materials.

Description

technical field [0001] The invention belongs to the technical field of semiconductor integrated circuits, and in particular relates to a mixed crystal plane strained Si and strained SiGe planar BiCMOS integrated device and a preparation method. Background technique [0002] In the contemporary era of highly developed information technology, microelectronic technology represented by integrated circuits is the key to information technology. As the fastest-growing, most influential and most widely used technology in human history, integrated circuits have become an important symbol to measure a country's scientific and technological level, comprehensive national strength and national defense strength. [0003] The "Moore's Law" that has had a huge impact on the development of the microelectronics industry points out that: the number of transistors on an integrated circuit chip doubles approximately every 18 months, and the performance also doubles; for more than 40 years, the w...

Claims

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Application Information

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Patent Type & AuthorityPatents(China)
IPC IPC(8): H01L27/06H01L21/8249
Inventor胡辉勇宋建军王斌张鹤鸣宣荣喜舒斌戴显英郝跃
OwnerXIDIAN UNIV