Metal-oxide-semiconductor field-effect transistor layout structure

Abstract

Disclosed is a metal-oxide-semiconductor field-effect transistor layout structure, which employs a common drain area having a right cross-shaped pattern and at least two common drain areas having tartan design, and a mixed array having a right cross-shaped pattern common drain area and a right cross-shaped pattern common source electrode which are formed by a common source electrode area having a right cross-shaped pattern and at least two common source electrode areas having tartan design. The metal-oxide-semiconductor field-effect transistor layout structure can improve the assembly density of the conventional layout circuit and promote the width of the efficient information channel thereof, thereby realizing the objective of reducing the cost and operation with higher power.

Description

technical field [0001] The invention relates to a layout structure of a metal oxide half field effect transistor, in particular to a layout structure of a metal oxide half field effect transistor with a higher effective channel width and a higher component density, which can increase the component density of a traditional layout circuit and improve its Effective channel width for lower cost and higher power operation. Background technique [0002] In recent years, Metal Oxide Semiconductor (MOS) has achieved the purpose of increasing device speed and driving current by reducing the size of the device. near the limit. Therefore, it is becoming more and more difficult to achieve performance improvement by reducing the size of components. [0003] In addition, Metal Oxide Semiconductor Field Effect Transistors (Power MOS) with large line widths are also widely used as power switches for power management applications. However, the excessively long connecting wires of the sour...

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Problems solved by technology

Generally speaking, it has (1) whether the corners of the source 120 and the

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