Processor Architecture and Instruction Execution Method Combining Sequence and VLIW

Abstract

The invention discloses a processor architecture and instruction execution method integrating a sequence and a VLIW (Very Long Instruction Word). A VLIW distribution unit and a sequence execution distribution unit are additionally arranged between a processor instruction fetching unit and a decoding unit, a currently fetched instruction is determined to flow to one distribution unit through an execution mode selection switch controlled by an execution mode switching instruction, if the currently fetched instruction flows to the VLIW distribution unit, preset parallel information in instruction coding is identified by hardware, parallel instructions are sequentially distributed by groups; and if the currently fetched instruction flows to the sequence execution distribution unit, the hardware carries out data dependency judgment and physical resource limit judgment among the instructions, maintains a register dependence table executing the instructions, and determines that which instructions can be distributed and which instructions can be distributed after former calculation waited to be completed. According to the invention, two instruction distribution units are realized inside the same processor, and two execution modes can be freely switched according to different application demands.

Description

technical field [0001] The invention belongs to the field of processor architecture, and relates to a processor architecture and an instruction execution method combining sequence and VLIW. Background technique [0002] In the process of executing the program, the processor adopting the von Neumann or Harvard structure continuously loads executable instructions from the external memory and executes them inside the processor. These executable instructions are generated by software and stored in binary executable files. There are a lot of data dependencies between these executable instructions, for example, some calculations need to use the results of other calculations. There are many ways to determine the data dependency and parallelism between adjacent instructions, some are determined by hardware, and some are determined by software. These methods also directly affect the development of assembler programs and are part of the software-hardware interface. [0003] When the...

AI Technical Summary

Problems solved by technology

[0006] In existing processors, only a single architecture is usually used

Processors that use sequential instruction execution are mainly for general-purpose processing, and are often insufficient in computing performance

However, processors using ultra-long instruction word execution mode are mainly oriented to the field of digital signal processing, and are weak in compatibility and general processing.

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