Bit line structure and manufacturing method thereof
A manufacturing method and bit line technology, applied in semiconductor/solid-state device manufacturing, electrical components, transistors, etc., can solve problems such as unfavorable semiconductor process development, and achieve the effect of reducing parasitic capacitance and reducing spacing
Active Publication Date: 2012-12-19
WINBOND ELECTRONICS CORP
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Problems solved by technology
Therefore, in order to reduce the parasitic capacitance, a larger interval is required between the bit line and the bit line, or a thicker insulating layer 110 is used to isolate the bit line 102a and the semiconductor substrate 100, which is not conducive to the development of more advanced semiconductor processes.
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[0029] In order to make the above and other objects, features, and advantages of the present invention more comprehensible, preferred embodiments are listed below and described in detail in conjunction with the accompanying drawings.
[0030] See figure 2 , which is a top view of a DRAM provided by an embodiment of the present invention. In a semiconductor substrate 200, a plurality of trenches for bit lines 202 and a plurality of trenches for word lines 204 are included, which are substantially vertically and alternately arranged. The groove formed by each bit line 202 contains a bit line 202, and the groove formed by each word line contains a word line 204, wherein the word line 204 is divided into two left and right (such as figure 2 shown). The active region 206 of this transistor is an unrecessed region, thus forming a pillar. Each bit line 202 and word line 204 is electrically connected to the active area of the transistor, and provides input / output signals throug...
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The invention discloses a bit line structure and a manufacturing method of the bit line structure. The bit line structure comprises a base material, an insulating layer, a conducting material, and a wire, wherein a bottle-shaped groove is arranged in the base material, and comprises a first groove and an expanded second groove, the first groove and the second groove are respectively provided with a first side wall and a second side wall which are opposite to each other, both the first side wall of the first groove and the first side wall of the second groove are located on the same side of the bottle-shaped groove; the insulating layer is located in the second groove, is provided with a first opening towards the first groove and forms a second opening with the second groove, the second opening is connected to the first opening, and the top part of the first side wall of the second groove is exposed; the conducting material is at least located at a part of the base material which is adjacent to the second opening; the wire is located in the first opening and is in direct contact with the conducting material. The bit line structure and the manufacturing method can effectively reduce the parasitic capacitance between the bit lines and cannot increase the minimum interval between the bit lines.
Description
technical field [0001] The present invention relates to semiconductor devices, and more particularly to a dynamic random access memory and a manufacturing method thereof. Background technique [0002] At present, the dynamic random access memory (DRAM) industry has developed an embedded bit line structure, and the bit line is fabricated in a substrate to reduce the size of the memory. At present, the industry has also introduced the structure of vertical transistors. In a vertical transistor structure, the active region of the transistor is formed in a single crystal semiconductor substrate. A storage capacitor is formed on top of the active area. The bit line and the word line are buried in the semiconductor substrate, and each bit line and word line are electrically connected with the active area of the transistor, and control the change of charge in the storage capacitor through the bit line and the word line. [0003] Currently, there are various methods of forming ...
Claims
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IPC IPC(8): H01L21/8242H01L27/108H10B12/00
Inventor 郭泽绵
Owner WINBOND ELECTRONICS CORP