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Territory generating method and system for reinforcing reliability of semiconductor metal layer

A metal layer and reliability technology, which is applied in the field of layout generation methods and systems for enhancing the reliability of semiconductor metal layers, can solve problems such as uneven current distribution, achieve the goal of overcoming uneven current distribution, avoiding design rule violations, and enhancing reliability Effect

Active Publication Date: 2015-03-04
INST OF MICROELECTRONICS CHINESE ACAD OF SCI
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Problems solved by technology

[0005] Embodiments of the present invention provide a layout generation method and system for enhancing the reliability of a semiconductor metal layer, which can overcome problems such as uneven current distribution generated during the metal drilling process

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  • Territory generating method and system for reinforcing reliability of semiconductor metal layer
  • Territory generating method and system for reinforcing reliability of semiconductor metal layer
  • Territory generating method and system for reinforcing reliability of semiconductor metal layer

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Embodiment Construction

[0055] In order for those skilled in the art to further understand the features and technical contents of the present invention, please refer to the following detailed description and accompanying drawings of the present invention. The accompanying drawings are provided for reference and illustration only, and are not intended to limit the present invention.

[0056] The technical solutions of the present invention will be described below in conjunction with the drawings and embodiments.

[0057] see figure 1 , is an embodiment of a layout generation method for enhancing the reliability of a semiconductor metal layer according to an embodiment of the present invention.

[0058] The method can include:

[0059] Step 101 , receiving the size data of large-area metal and metal holes, and the row spacing and column spacing data of the metal holes.

[0060] First, the system receives preset size data of large-area metal and metal holes, which can be length and width, as well as r...

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Abstract

The invention provides a territory generating method and a system for reinforcing reliability of a semiconductor metal layer. The method comprises the following steps of: receiving dimensional data of large-area metal and metal holes as well as line spacing data and column spacing data of the metal holes; determining a line number and a column number of the metal holes according to the dimensional data of the large-area metals and metal holes and the line spacing data and the column spacing data of the metal holes; obtaining a line spacing corrected value and a column spacing corrected value of the metal holes according to the ling number and the column number of the metal holes and the dimensional data of the large-area metal and the metal holes, and correcting the line spacing data and the column spacing data of the metal holes; generating a metal punch template according to the dimensional data of the large-area metal and the metal holes and the line spacing corrected value and the column spacing corrected value of the metal holes; and punching the large-area metal according to the metal punch template. The territory generating method and the system are capable of overcoming the problem such as nonuniform current, and the like generated in the metal punching process.

Description

technical field [0001] The invention relates to the technical field of semiconductors, in particular to a layout generation method and system for enhancing the reliability of a semiconductor metal layer. Background technique [0002] In the layout design of integrated circuits, large-area metals often appear, that is, large-area metals are longer in length and wider in width (above 30um×30um). For example, paths with large currents such as the total power supply interconnection and ground interconnection in the chip must use wide metal wiring; in order to ensure the flatness of the chip, a large area of ​​​​redundant metal is inserted in the spare area of ​​​​the chip, etc. [0003] However, when using a large area of ​​metal, there are also some problems: on the one hand, a large area of ​​metal brings a large parasitic capacitance, which easily leads to excessive accumulation of charges; on the other hand, a large metal mask will cause the etched relief to appear Moreover...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G06F17/50
Inventor 尹明会陈岚赵劼
Owner INST OF MICROELECTRONICS CHINESE ACAD OF SCI
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