Looking for breakthrough ideas for innovation challenges? Try Patsnap Eureka!

Systems, methods, and devices for cache block coherence

A cache and cache line technology, applied in the direction of memory system, memory architecture access/allocation, memory address/allocation/relocation, etc.

Active Publication Date: 2013-01-16
APPLE INC
View PDF1 Cites 24 Cited by
  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

For example, general-purpose processing on a GPU may require writing specialized programs with explicit memory buffer management, which can be onerous and tedious work for software developers

Method used

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
View more

Image

Smart Image Click on the blue labels to locate them in the text.
Viewing Examples
Smart Image
  • Systems, methods, and devices for cache block coherence
  • Systems, methods, and devices for cache block coherence
  • Systems, methods, and devices for cache block coherence

Examples

Experimental program
Comparison scheme
Effect test

Embodiment Construction

[0030] One or more specific embodiments of the present disclosure will be described below. These described embodiments are merely examples of the presently disclosed technology. Furthermore, in an effort to provide a concise description of these embodiments, all features of an actual implementation may not be described in the specification. It should be recognized that in the development of any such practical implementation, as in any engineering or design project, many implementation-specific decisions must be made to achieve the developer's specific goals, such as compliance with system-related and business associated limitations, which may vary by implementation. Furthermore, it should be appreciated that such a development effort might be complex and time consuming, but would undoubtedly be a routine undertaking of design, fabrication, and production for those of ordinary skill in the art having the benefit of this disclosure.

[0031] When introducing elements of variou...

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

PUM

No PUM Login to View More

Abstract

Systems, methods, and devices for efficient cache coherence between memory-sharing devices 12A and 12B are provided. In particular, snoop traffic may be suppressed based at least partly on a table of block tracking entries (BTEs). Each BTE may indicate whether groups of one or more cache lines of a block of memory could potentially be in use by another memory-sharing device 12A and 12B. By way of example, a memory-sharing device 12 may employ a table of BTEs 56 that each has several cache status entries. When a cache status entry indicates that none of a group of one or more cache lines could possibly be in use by another memory-sharing device 12, a snoop request for any cache lines of that group may be suppressed without jeopardizing cache coherence.

Description

technical field [0001] The present disclosure relates generally to cache coherency, and more specifically to techniques for efficiently maintaining cache coherency between devices by tracking whether one or more cache lines are likely to be in use. Background technique [0002] This section is intended to introduce the reader to various aspects of technology, which may be related to various aspects of the technology that are described and / or claimed below. This discussion is considered helpful in providing the reader with background information in order to better understand the various aspects of the disclosure. Accordingly, it should be understood that these statements are to be read in light of this and not as admissions of prior art. [0003] Electronic devices with multiple processors or other memory sharing devices frequently use cache coherency techniques to maintain the integrity of the shared memory. Common cache coherency techniques may involve bus snooping, where...

Claims

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

Application Information

Patent Timeline
no application Login to View More
Patent Type & Authority Applications(China)
IPC IPC(8): G06F12/08
CPCG06F2212/301G06F12/0831G06F2212/302G06F12/08G06F15/167
Inventor I·C·亨德瑞J·格尼恩
Owner APPLE INC
Who we serve
  • R&D Engineer
  • R&D Manager
  • IP Professional
Why Patsnap Eureka
  • Industry Leading Data Capabilities
  • Powerful AI technology
  • Patent DNA Extraction
Social media
Patsnap Eureka Blog
Learn More
PatSnap group products

Browse by: Latest US Patents, China's latest patents, Technical Efficacy Thesaurus, Application Domain, Technology Topic, Popular Technical Reports.

© 2024 PatSnap. All rights reserved.Legal|Privacy policy|Modern Slavery Act Transparency Statement|Sitemap|About US| Contact US: help@patsnap.com