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Synchronous phasor calculation method based on discrete Fourier transform (DFT) recursion of field programmable gate array (FPGA) hardware

A technology of synchronized phasors and calculation methods, applied in calculation, special data processing applications, instruments, etc., can solve the problems of unfavorable master station data processing, large calculation result error, high CPU load, etc.

Active Publication Date: 2013-01-30
NANJING GUODIAN NANZI POWER GRID AUTOMATION CO LTD
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Problems solved by technology

Such traditional processing methods often lead to high CPU load, and the synchrophasor data packets sent to the master station may not be sent evenly, which is not conducive to the data processing of the master station
A

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  • Synchronous phasor calculation method based on discrete Fourier transform (DFT) recursion of field programmable gate array (FPGA) hardware
  • Synchronous phasor calculation method based on discrete Fourier transform (DFT) recursion of field programmable gate array (FPGA) hardware
  • Synchronous phasor calculation method based on discrete Fourier transform (DFT) recursion of field programmable gate array (FPGA) hardware

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[0066] In order to make the technical means, creative features, objectives and effects of the present invention easy to understand, the following is attached figure 1 And figure 2 , Further explain the present invention.

[0067] See figure 1 with figure 2 , The present invention is a method for calculating synchronous phasor based on FPGA hardware DFT recursion, which is characterized in that the method includes the following steps:

[0068] (1) FPGA and CPU are connected by 32-bit or 64-bit parallel bus 1 in hardware. FPGA has an interrupt signal connected to the external interrupt pin of CPU. FPGA accesses standard clock 1PPS signal and B code time signal, FPGA passes Parallel bus 2 controls the AD chip;

[0069] (2) Define sampling configuration register (CONFIG_REG), sampling buffer register (DATA_REG), DFT coefficient original register (DFT_COEF), DFT result buffer register (DFT_REG) on the FPGA side;

[0070] (3) The CPU writes the predefined DFT coefficients into the prede...

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Abstract

The invention relates to a synchronous phasor calculation method based on DFT recursion of FPGA hardware. An FPGA is configured through a central processing unit (CPU) and controls an analog-digital (AD) converter to complete a sampling process under the 1 pulse per second signal (1PPS) synchronization, and the cycle DFT calculation and the recursion DFT calculation are utilized for eliminating accumulated errors of the recursion DFT calculation; and a complex phasor compensation algorithm is completed by the CPU. The FPGA and the CPU are matched to complete an acquisition calculation compensation process of synchronous phasors, and both the high-speed parallel computing capability of the FPGA and the flexible floating-point operation function of the CPU are used. The recursion DFP operation which is long in consumed time is completed by the FPGA, and the CPU loads are small, so that the communication response instantaneity of the CPU is guaranteed, and further, the communication reliability of a power management unit (PMU) is improved.

Description

technical field [0001] The invention discloses a synchrophasor calculation method based on FPGA hardware DFT recursion, belonging to the technical field of power system automatic measurement. Background technique [0002] With the continuous development of my country's power grid construction, the grid structure is becoming more and more perfect and more complex. There is an urgent need for new technical means to strengthen the dynamic security monitoring capabilities of the power grid and improve the security and stability of the power grid. The traditional SCADA system collects steady-state data refreshed at the second level, and the fault recorder provides fast transient waveform data within a period of time before and after the fault. There is no way to provide dynamic phasor data collected synchronously across the entire network. The synchronized phasor measurement unit (PMU) uses the satellite synchronous clock system to provide uniform sampling pulse and standard time...

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Application Information

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IPC IPC(8): G06F19/00
Inventor 温富光陈庆旭
Owner NANJING GUODIAN NANZI POWER GRID AUTOMATION CO LTD
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