Message data transmission method, bridging module, read module and message data transmission system for peripheral component interconnect express (PCIe) interfaces

Abstract

The application discloses a message data transmission method, a bridging module, a read module and a message data transmission system for peripheral component interconnect express (PCIe) interfaces, wherein the method comprises the following steps of: setting corresponding pointer spaces in a central processing unit (CPU) memory in a bridging module terminal for every PCIe interface; and writing write pointers into the pointer spaces corresponding to every PCIe interface through every PCIe interface. According to the application, because the pointers in every pointer space are the same until the message data are written into a cache block of the CPU memory through the PCIe interfaces and a descriptor package is written into a receive queue of the CPU through the PCIe interfaces, the mode of reading the pointers to acquire the message data only when the pointers in every pointer space are the same can be used to effectively avoid message data read errors caused by the fact that the writing of the pointers is earlier than the two steps because of different time delays of different PCIe interfaces when the bridging module supports multi-path PCIe interface data transmission.

Description

technical field [0001] The invention relates to the field of computers, and more specifically, relates to a method for transmitting message data of a PCIe interface, a bridge module, a reading module and a system. Background technique [0002] The PCIe interface is an important interface for interconnecting the X86CPU and other devices. The bridge module can complete the conversion between high-speed interfaces such as the XAUI interface and the PCIe interface. [0003] Such as figure 1 As shown, in the conversion process between the XAUI interface and the PCIe interface through the bridge module, after the bridge module receives the message data of the XAUI interface, it needs to perform the following three operations: [0004] S11. A CPU memory cache block is assigned to the message data, and the message data is written into the CPU memory cache block through the PCIe interface; [0005] S12, constructing a packet descriptor comprising the first address of the CPU memory...

AI Technical Summary

Problems solved by technology

[0008] The PCIe interface bridge module is generally implemented by FPGA devices. It is assumed that the maximum effective bandwidth that the PCIe interface of the FPGA device can provide is Gen1*4 mode, that is, 2.5G*4*0.8=8Gbps. When the bridge module is required to provide a larger When connecting high-bandwidth devices, for example, when connecting with an XAUI interface, since the effective bandwidth that one can provide is less than the required bandwidth, in order to improve the bandwidth of the PCIe interface, the prior art generally selects high-end FPGA devices For example, choose an FPGA device that can support PCIe Gen1*8 or PCIe Gen2*4, but the disadvantage of choosing a high-end FPGA device to improve the bandwidth of the PCIe interface is that the cost is relatively high

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