Method and device for increasing utilization rate of FPGA (field programmable gate array) memory

Abstract

The invention relates to a method and a device for increasing a utilization rate of an FPGA (field programmable gate array) memory by means of length and width transformation. The method includes S1, inputting an original datum; S2, segmenting the width of the original datum to obtain a plurality of segmented data and storing the segmented data in the block memory; and S3, reading the segmented data from the block memory, splicing the segmented data into the original datum and outputting the original datum. The method and the device have the advantages that internal data buses of an FPGA are transformed by the aid of an internal high-speed clock, so that the length of the memory is transformed, limitation on the length and the width of the internal block memory of the FPGA is sufficiently utilized, the utilization rate of the internal block memory of the FPGA is increased, and relevant logic consumption is low.

Description

technical field [0001] The invention relates to the field of Ethernet, in particular to a method for improving the utilization rate of FPGA internal memory through length transformation and a device for realizing the method. Background technique [0002] When using FPGA to do the hardware simulation of the Ethernet engine, it often encounters the realization problem of very short and wide FIFO. [0003] In a kind of prior art, the storage or reading of very large width FIFO is realized by splicing on the width of a plurality of blocks of block memory, this method is owing to only splicing on the width, so on block memory length (depth) The utilization rate of the FPGA is extremely low, and if processing multiple FIFOs of this type, the resources of the block memory inside the FPGA will be occupied a lot, and even the number of block memories inside the FPGA cannot meet the number required to realize this type of FIFO. [0004] Another prior art is to realize the storage or ...

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Problems solved by technology

[0004] Another existing technology is to realize the storage or reading of a long-width FIFO by splicing the look-up table LUT inside the FPGA. This method consumes a large amount of wiring resources because the fan-out of the address lines is too large.

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