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Logic optimizing and parallel processing method of integrated circuit

A parallel processing and logic optimization technology, applied in electrical digital data processing, special data processing applications, instruments, etc., can solve problems such as load balancing problem improvement, and achieve the effect of reducing parallel processing time and improving processing efficiency

Active Publication Date: 2013-04-10
江苏博沃汽车电子系统有限公司
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AI Technical Summary

Problems solved by technology

Jiang Hanyang and others proposed a QoS guided Min-min algorithm based on task priority, and analyzed and compared it with the Min-min algorithm and QoS guided Min-min algorithm through simulation experiments, and found that the algorithm is better, but it retains the load balancing problem. further improvement of

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  • Logic optimizing and parallel processing method of integrated circuit
  • Logic optimizing and parallel processing method of integrated circuit
  • Logic optimizing and parallel processing method of integrated circuit

Examples

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example

[0040] There is a logic function F(x) with four inputs and eight outputs,

[0041] f 1 = x 2 ‾ x 3 x 4 + x 1 ‾ x 3 ‾ x 4 ‾ + x 1 x 2 x 3 ...

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Abstract

The invention discloses a logic optimizing and parallel processing method of an integrated circuit. The parallel processing has a function in the logic optimizing that a multiple input and multiple output logic matrix is divided into a plurality of multiple input and single output logic matrixes, and then the multiple input and single output logic matrixes are dispatched to processing nodes to realize optimizing and processing; the optimizing and the processing combine the scale of a logic in the logic optimizing process and the combining probability of implication items in the logic, so as to form a parallel processing dispatching algorithm; the dispatching process of the logic optimizing and the parallel processing is divided into sections, and the inside of each section follows the logic with longer priority dispatching and processing time; and a distribution strategy is adopted in the logic optimizing and parallel processing of the integrated circuit. The logic optimizing and parallel processing method has the advantage that according to the number of the implication items in a logic function of the integrated circuit and the correlation degree of the implication items, the processing efficiency of the logic optimizing of the integrated circuit can be improved.

Description

technical field [0001] The invention relates to a parallel processing method for integrated circuit logic optimization. Background technique [0002] Since there is almost no research on task scheduling in integrated circuit logic optimization parallel processing in domestic and foreign journals, conference papers, books, etc., it is necessary to study parallel processing scheduling algorithms and logic optimization on the basis of two fields , combined with the characteristics of logic optimization, a parallel processing scheduling algorithm suitable for logic optimization is formed. [0003] With the development of EDA, the number of logic function variables and states of integrated circuits is increasing, and traditional logic function simplification methods, such as formula method and Karnaugh map method, can no longer satisfy the work of optimizing integrated circuits. The unintuitiveness of the formula method makes it difficult to determine whether the simplification ...

Claims

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Application Information

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IPC IPC(8): G06F17/50
Inventor 邱建林陈建平顾翔陈莉潘阳杨娜
Owner 江苏博沃汽车电子系统有限公司
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