A kind of fir filter filtering method and filter

A filter and sub-filter technology, applied in the information field, can solve the problems of increasing the bit width of the multiplier, limiting the application of the filter, and not being directly applicable to the parallel FIR filter.

Inactive Publication Date: 2016-06-15
HUAWEI TECH CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0005] 1. The bit width of some multipliers of the filter increases greatly, which makes the processing delay of the filter larger, which seriously limits the application of this filter in adaptive equalizers
[0006] 2. The length of the processing path from each input data to the calculation of the filtering result is very different. It is necessary to insert unnecessary registers on the path with a shorter processing path length, which causes unnecessary waste of resources.
[0007] 3. Both filter structures use register operations, so they cannot be directly applied to parallel FIR filters for downsampling

Method used

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  • A kind of fir filter filtering method and filter
  • A kind of fir filter filtering method and filter
  • A kind of fir filter filtering method and filter

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Effect test

Embodiment 1

[0063] An embodiment of the present invention provides an FIR filter filtering method, wherein the order of the filter coefficient vector H(n) of the filter is N, and the length of the input data vector X(m) is M. Specifically, as figure 1 As shown, the method includes:

[0064] 101. A first multiplier included in the filter is used to obtain (X(m)+X(m+Q))*(H(n)+H(n+Q)).

[0065] where 1<=Q<=N.

[0066] 102. The filter is further used to obtain X(m)*H(n+Q) and X(m+Q)*H(n).

[0067] 103. The filter, according to the obtained (X(m)+X(m+Q))*(H(n)+H(n+Q)), X(m)*H(n+Q) and X(m+Q)*H(n) to obtain X(m)*H(n)+X(m+Q)*H(n+Q).

[0068] The purpose of the present invention is to obtain X(m)*H(n+Q), X(m+Q)*H(n), X(m)*H(n)+X(m) in the prior art +Q)*H(n+Q) requires four multipliers to realize, that is, as figure 2 shown.

[0069] In this scheme, X(m) and X(m+Q), as well as H(n) and H(n+Q) are combined and added together and then multiplied by the first multiplier M1 to obtain X(m)*H (n...

Embodiment 2

[0084] The embodiment of the present invention provides a method for FIR filter filtering. The method is specifically as follows: the order of the filter coefficient vector H(n) is N to be 8, the length of the input data vector X(m) is 24, and the downsampled The multiple L is 2, and Q is 2 as an example for detailed description. At this time, the filter includes the first sub-filter to the ninth sub-filter. Specifically, such as Figure 5 As shown, the method includes:

[0085] 501. The p-th sub-filters of the first to ninth sub-filters respectively include four first multipliers, wherein the j-th first multiplier among the four first multipliers The device obtains (X(L*(p-1)+j+[j / 2]*2)+X(L*(p-1)+j+[j / 2]*2+Q))*(H(j+ [j / 2]*2)+H(j+[j / 2]*2+Q)).

[0086] Wherein, j is i, i+1, i is an even number, and i>=0, p is an even number, and p<=(M-N+L) / L.

[0087] 502. The p-th sub-filter is also used to obtain X(L*(p-1)+j+[j / 2]*2)*H(j+[j / 2]*2+Q) and X(L *(p-1)+j+[j / 2]*2+Q)*H(j+[j / 2]*2...

Embodiment 3

[0160] An embodiment of the present invention provides an FIR filter, wherein the order of the filter coefficient vector H(n) of the filter is N, the length of the input data vector X(m) is M, and the downsampling multiple is L , specifically, such as Figure 16 As shown, the filter includes the first sub-filter to the (M-N+L) / L sub-filter, wherein,

[0161] The filter comprises a first multiplier M1 for obtaining (X(m)+X(m+Q))*(H(n)+H(n+Q)), where , 1<=Q<=N;

[0162] The filter is also used to obtain X(m)*H(n+Q) and X(m+Q)*H(n) respectively;

[0163] The filter, according to the obtained (X(m)+X(m+Q))*(H(n)+H(n+Q)), X(m)*H(n+Q) and X( m+Q)*H(n), obtain X(m)*H(n)+X(m+Q)*H(n+Q) respectively.

[0164] Further, if Q=2, and the downsampling multiple of the filter is L=2, the filter includes the first sub-filter to the (M-N+L) / L sub-filter ;

[0165]Wherein, the p-th sub-filter from the first sub-filter to the (M-N+L) / L-th sub-filter includes N / 2 of the first multipliers, whe...

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Abstract

The utility model provides a filtering method of a far-infra-red (FIR) filter and a filter. On the basis that multiplying units in the filter can be reduced, bit width of the multiplying units is enabled to increase slightly, time delay from data being input to various processing paths of the filtering results are basically the same, and the method can be applicable to a down sampling parallel FIR filter. A first multiplying unit of the filter is used for acquiring ( X ( m )+ X (m+Q)) * (H ( n ) + H (n + Q) ), wherein the value of Q is between 1 and N, and the filter is further used for acquiring X ( m ) * H ( n + Q ) and X ( m + Q) * H ( n ). According to the acquired ( X ( m ) + X ( m + Q) ) * ( H (n) + H ( n + Q) ), X ( m ) * H ( n + Q ) and X ( m + Q ) * H ( n ), the filter acquires X ( m ) * H ( n ) + X ( m + Q ) * H ( n + Q ). The filtering method of the FIR filter and the filter are applicable to the technical field of the filters.

Description

technical field [0001] The present invention relates to the field of information technology, and in particular, to a method and filter for filtering an FIR filter. Background technique [0002] Finite Impulse Response FIR (Finite Impulse Response) filter has been widely used in modern wireless, microwave, optical communication and satellite communication fields due to its excellent linear phase characteristics and unconditional stability. In recent years, due to people's higher and higher requirements for data communication bandwidth, in order to improve data throughput, parallel FIR filters have been more and more widely used in digital communication systems, and the degree of parallelism is getting higher and higher. [0003] However, due to the existence of a large number of multipliers in the highly parallel FIR filter, it takes up a lot of hardware resources in the implementation of FPGA or ADIC, which increases the power consumption of the system. Commonly used parall...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H03H17/02
Inventor 王文昌郑扬牛宏伟
Owner HUAWEI TECH CO LTD
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