Structure for implementing DFT of 32-channel parallel data

A data, even number technology, applied in the field of 32-channel parallel data DFT implementation structure, can solve the problems such as the inability of analog processing to realize variable speed, the inability to realize serial digital demodulation, and the inability of sampling clock to be directly sent to FPGA.
CN101741801AActive Publication Date: 2010-06-16XIAN INSTITUE OF SPACE RADIO TECH
3 Cites 4 Cited by

Patent Information

Authority / Receiving Office
CN · China
Current Assignee / Owner
XIAN INSTITUE OF SPACE RADIO TECH
Publication Date
2010-06-16

Smart Images

  • Figure 1
    Figure 1
  • Figure 2
    Figure 2
  • Figure 3
    Figure 3
Patent Text Reader

Abstract

The invention relates to a structure for implementing discrete Fourier transform (DFT) of 32-channel parallel data. In the invention, firstly, a full parallel structure is adopted, 32-channel parallel data is splitted into two 8-channel parallel data and a 16-channel data according to parity, secondly, a radix-2 butterfly algorithm is adopted to process the 8-channel parallel data, a radix-4 butterfly algorithm is utilized to process the 16-channel parallel data, finally the processed results of two 8-channel parallel data are multiplied by a constant coefficient, and addition and subtractionoperations are carried out with the processed result of the 16-channel parallel datum to obtain a DFT result of the 32-channel parallel data. The structure for implementing 32-channel parallel data DFT filters in a frequency domain, directly crosses over products, reduces delay time and amount of multipliers compared with a time domain multi-item filter method, decreases a processing scale of a field programmable gate array (FPGA) at the same time, improves hardware processing speed, is very suitable for processing high-speed and real-time digital signals, and can save hardware resource. The implementing structure can be completely utilized for carrying out inverse discrete Fourier transform (IDFT) on 32-channel parallel data.
Need to check novelty before this filing date? Find Prior Art

Description

technical field

[0001] The invention relates to a realization structure of 32-way parallel data DFT, which is mainly used in the field of high-speed digital processing, especially in the field of high-speed digital demodulators and modulators. Background technique

[0002] For high-speed modulators, analog modulators are gradually developing towards digital modulators due to the flexibility of digital implementations such as shaping filtering and pre-distortion. The shaping filter in the high-speed digital modulator is divided into parallel look-up table and digital direct realization according to its implementation method. Since a parallel look-up table can only correspond to one shaping coefficient, for variable shaping coefficients, it is necessary to make many tables. It may not necessarily meet the requirements, which is not easy for FPGA implementation. However, the digital direct realization method has almost no influence on the realization of the variable molding co...

Claims

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More