Structure for implementing DFT of 32-channel parallel data

A data, even number technology, applied in the field of 32-channel parallel data DFT implementation structure, can solve the problems such as the inability of analog processing to realize variable speed, the inability to realize serial digital demodulation, and the inability of sampling clock to be directly sent to FPGA.

Active Publication Date: 2010-06-16
XIAN INSTITUE OF SPACE RADIO TECH
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Problems solved by technology

Since the analog processing method cannot achieve variable speed, and its debugging is more complicated, it has been gradually replaced by digital demodulation
For the demodulation of QPSK modulation signals with a code rate up to 600Mbps

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  • Structure for implementing DFT of 32-channel parallel data
  • Structure for implementing DFT of 32-channel parallel data
  • Structure for implementing DFT of 32-channel parallel data

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Embodiment Construction

[0031] The present invention will be further described in detail below in conjunction with the accompanying drawings and specific embodiments.

[0032] figure 1 For the specific application method of high bit rate QPSK digital demodulation DFT / IDFT, the digital demodulator uses high-speed AD sampling, the data sent by AD is extracted by 16 times, overlapped and transformed into 32 channels of data, and 32 channels of data are processed after digital down-conversion DFT calculation, then filtering in the frequency domain, IDFT output after filtering, and then parallel clock recovery and carrier recovery to complete data demodulation. After the data is extracted by 16 times, the internal data processing speed is only 1 / 16 of the input, and the internal data processing of the high code rate QPSK demodulator is only 1 / 16 of the sampling clock, so it is very suitable for ultra-high code rate demodulation.

[0033] Since IDFT is the inverse transform of DFT, the embodiment of the p...

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Abstract

The invention relates to a structure for implementing discrete Fourier transform (DFT) of 32-channel parallel data. In the invention, firstly, a full parallel structure is adopted, 32-channel parallel data is splitted into two 8-channel parallel data and a 16-channel data according to parity, secondly, a radix-2 butterfly algorithm is adopted to process the 8-channel parallel data, a radix-4 butterfly algorithm is utilized to process the 16-channel parallel data, finally the processed results of two 8-channel parallel data are multiplied by a constant coefficient, and addition and subtractionoperations are carried out with the processed result of the 16-channel parallel datum to obtain a DFT result of the 32-channel parallel data. The structure for implementing 32-channel parallel data DFT filters in a frequency domain, directly crosses over products, reduces delay time and amount of multipliers compared with a time domain multi-item filter method, decreases a processing scale of a field programmable gate array (FPGA) at the same time, improves hardware processing speed, is very suitable for processing high-speed and real-time digital signals, and can save hardware resource. The implementing structure can be completely utilized for carrying out inverse discrete Fourier transform (IDFT) on 32-channel parallel data.

Description

technical field [0001] The invention relates to a realization structure of 32-way parallel data DFT, which is mainly used in the field of high-speed digital processing, especially in the field of high-speed digital demodulators and modulators. Background technique [0002] For high-speed modulators, analog modulators are gradually developing towards digital modulators due to the flexibility of digital implementations such as shaping filtering and pre-distortion. The shaping filter in the high-speed digital modulator is divided into parallel look-up table and digital direct realization according to its implementation method. Since a parallel look-up table can only correspond to one shaping coefficient, for variable shaping coefficients, it is necessary to make many tables. It may not necessarily meet the requirements, which is not easy for FPGA implementation. However, the digital direct realization method has almost no influence on the realization of the variable molding co...

Claims

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Application Information

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IPC IPC(8): H04L27/26
Inventor 杨光文杨新权李立谢耀菊陈安和
Owner XIAN INSTITUE OF SPACE RADIO TECH
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