Anti-false-triggering power supply clamp ESD (Electro-Static Discharge) protection circuit

Abstract

The invention discloses an anti-false-triggering power supply clamp ESD (Electro-Static Discharge) protection circuit, which comprises an ESD impact detection part, a bleeding transistor, a bleeding transistor turning-on circuit and a bleeding transistor turning-off circuit. The anti-false-triggering power supply clamp ESD protection circuit has the advantages that the static charge bleeding capacity is very strong during ESD impact under the situation of small layout area, the leakage current is very small during normal electrification and the false triggering immunity is very strong during rapid electrification.

Description

technical field [0001] The invention relates to the field of integrated circuit chip electrostatic discharge (Electronic Static Discharge, ESD) protection technology, in particular to an anti-false trigger type power clamp ESD protection circuit. Background technique [0002] The electrostatic protection design of integrated circuit chips is one of the necessary conditions to ensure the reliable operation of chips. Electrostatic shock is ubiquitous in life. With the continuous advancement of integrated circuit technology, the size of the devices that make up the circuit is getting smaller and smaller. Electrostatic shock itself has the characteristics of short time and very large instantaneous current. When the device size is small Under normal circumstances, the electrostatic shock will form a huge equivalent electric field inside the device, which will directly break down the device, causing the device to suffer irreversible physical damage and be paralyzed. [0003] The ...

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Problems solved by technology

However, figure 1 The resistance of the turn-off path of the circuit shown is realized by the active device PMOS transistor. In the integrated circuit process, the resistance realized by the active device is usually difficult to achieve a large resistance value

in order to figure 1 If the detection capacitor resistance time constant of the circuit shown (that is, the product of the capacitance value of C1 and the resistance value of R1) is really small, then the time delay of the off-path of the bleeder transistor under the impact of ESD needs to be large enough, so that the passive capacitor C2 and C3 will be correspondingly large, making figure 1 The chip layout area of ​​the structure shown is greatly increased

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