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Method and system for integrated circuit longest measurable path selection test

An integrated circuit and path selection technology, applied in the direction of electrical digital data processing, special data processing applications, instruments, etc., can solve the problem of too much time spent on testability, reduce the number of tests, improve efficiency, and avoid the effect of backtracking

Active Publication Date: 2015-05-20
TSINGHUA UNIV
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  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

Every time a gate is expanded, it is necessary to judge whether the path is testable, and it takes too much time to judge the testability

Method used

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  • Method and system for integrated circuit longest measurable path selection test
  • Method and system for integrated circuit longest measurable path selection test
  • Method and system for integrated circuit longest measurable path selection test

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Embodiment Construction

[0050] The specific implementation manners of the present invention will be further described in detail below in conjunction with the accompanying drawings and embodiments. The following examples are used to illustrate the present invention, but are not intended to limit the scope of the present invention.

[0051] figure 1 It is a flowchart of an integrated circuit longest measurable path selection test method according to an embodiment of the present invention, including the following steps:

[0052] S1: Perform preprocessing on the integrated circuit to obtain all b-f segments in the integrated circuit, where the b-f segment refers to a pair of segments with a successor relationship and conflicting sensitization values;

[0053] Wherein, step S1 specifically includes the following steps:

[0054] S11: dividing the integrated circuit into several segments without fan-out;

[0055] S12: Scan the integrated circuit in units of segments starting from the segment starting fro...

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Abstract

The invention discloses a method and a system for integrated circuit longest measurable path selection test and relates to the technical field of digital integrated circuit test. An integrated circuit is preprocessed to obtain all b-f sections in the integrated circuit, so that backtracking is avoided, test number of part of paths is decreased during path selection, efficiency of integrated circuit longest path selection is improved greatly, and improvement of delay fault test efficiency is realized.

Description

technical field [0001] The invention relates to the technical field of digital integrated circuit testing, in particular to a method and system for selecting and testing the longest measurable path of an integrated circuit. Background technique [0002] In the field of digital circuit testing, there are many methods proposed for delay testing, and two main fault models are jump fault model and path delay fault model. The outgoing path required by the jump fault model is not required to be the longest path through the target gate, but if the jump fault is very small, the small delay fault (SDD) may escape the test because the outgoing path is too short , so it is necessary to propose some longest measurable path selection methods. [0003] Sharma and Patel proposed a method based on graph theory and ATPG-driven, which covers all the doors by selecting a small part of the longest path. Long paths, but this method is only suitable for selecting one longest path through each g...

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G06F17/50
Inventor 向东李建波随文杰
Owner TSINGHUA UNIV