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Failure testing method of embedded flash memory

A failure testing and embedded technology, applied in static memory, instruments, etc., can solve problems such as low test efficiency and long test time

Inactive Publication Date: 2013-05-08
SHANGHAI HUAHONG GRACE SEMICON MFG CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0009] The purpose of the present invention is to provide a failure test method for embedded flash memory, to solve the existing problems of long test time and low test efficiency of embedded flash memory, so as to achieve the purpose of improving test efficiency and reducing test cost

Method used

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  • Failure testing method of embedded flash memory
  • Failure testing method of embedded flash memory
  • Failure testing method of embedded flash memory

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Embodiment Construction

[0030] The failure testing method of the embedded flash memory proposed by the present invention will be further described in detail below in conjunction with the accompanying drawings and specific embodiments. Advantages and features of the present invention will be apparent from the following description and claims. It should be noted that all the drawings are in a very simplified form and use imprecise scales, and are only used to facilitate and clearly assist the purpose of illustrating the embodiments of the present invention.

[0031] figure 2 It is a flowchart of a failure testing method for an embedded flash memory according to an embodiment of the present invention.

[0032] Step 1: providing an embedded flash memory;

[0033] Such as image 3 As shown, the embedded flash memory includes a memory cell array 200, the memory cell array 200 includes m word lines 201, n bit lines 202 and s source lines 203, m, n and s are all greater than or equal to 1 an integer of ...

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Abstract

The invention provides a failure testing method of an embedded flash memory. The failure testing method comprises the following steps of: step 1, providing one embedded flash memory; and step 2, testing each memory cell of a diagonal line of a memory cell array. The embedded flash memory comprises the memory cell array, and the memory cell array comprises a plurality of word lines and a plurality of bit lines in cross arrangement with the word lines. By adopting the failure testing method of the embedded flash memory, combination of all of the word lines and the bit lines can be tested so long as the memory cell of the diagonal line of the memory cell array is tested. Compared with the prior art, by utilizing the failure testing method, the testing time can be effectively reduced so as to realize the purposes of improving the testing efficiency and reducing the testing cost.

Description

technical field [0001] The invention relates to the technical field of integrated circuit manufacturing, in particular to a failure testing method for an embedded flash memory. Background technique [0002] As we all know, the competition in the memory chip market is very fierce. Most domestic and foreign chip manufacturers have the ability to manufacture memory chips. Judging from the current trend, testing is one of the key factors affecting prices. How to improve test efficiency and reduce test cost is a very important issue under the premise of taking test reliability into consideration. [0003] Such as figure 1 As shown, the memory cell array 100 of the embedded flash memory is composed of a number of word lines (word lines) 101 and a number of bit lines (bit lines) 102 crossed. In order to check whether there is leakage or short circuit between the word line 101 and the intersecting bit line 102 . An early failure test (insert mortality test, IM test) needs to be p...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G11C29/12
Inventor 吴玮
Owner SHANGHAI HUAHONG GRACE SEMICON MFG CORP
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