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Multi-core processor system, control program and control method

A technology of multi-core processors and threads, applied in memory systems, multi-channel program devices, inter-program communication, etc., can solve data occupation and other problems

Inactive Publication Date: 2016-08-31
FUJITSU LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

That is, there is a problem that the distributed cache area of ​​the CPU is occupied by unread data

Method used

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  • Multi-core processor system, control program and control method
  • Multi-core processor system, control program and control method
  • Multi-core processor system, control program and control method

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Embodiment Construction

[0035] Preferred implementations of the multi-core processor system, control program and control method involved in the present invention will be described in detail. In addition, in the multi-core processor system of this embodiment, a multi-core processor refers to a processor on which a plurality of cores are mounted. As long as multiple cores are installed, it may be a single processor with multiple cores installed, or a processor group in which single-core processors perform parallel processing. In addition, in this embodiment, in order to simplify the description, a processor group in which single-core processors perform parallel processing is used as an example for description.

[0036] figure 1 It is an explanatory diagram showing an example of this embodiment. figure 1 Each code example is described in each {...} of thread 1 {...} and thread 2 {...}.

[0037] In thread 1, 5 is substituted into variable z, and 10 is substituted into variable x. Then, in thread 1, t...

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Abstract

The present invention relates to a multi-core processor system, a control program and a control method. When the OS ( 191 ) assigns the thread 2 to the CPU ( 102 ), the OS ( 191 ) sets the output data of the output data item as variable z, and the identification information of the input target thread of the identification information item of the input target thread is thread 2 The identification information of the allocation target CPU of the identification information item of the allocation target CPU is updated to the CPU (102). The OS ( 191 ) updates the identification information of the allocation target CPU of the identification information item of the allocation target CPU when the output data of the output data item is the variable x and the identification information of the input target thread of the identification information item of the input target thread is thread 2 for the CPU (102). When the OS ( 191 ) detects a write request for the variable x, the OS ( 191 ) uses the variable x as a search key to retrieve the identification information of the allocation target CPU of the identification information item of the allocation target CPU from the table, thereby determining the allocation target The identification information of the CPU stores the variable x in the distributed cache ( 112 ) of the CPU ( 102 ) based on the determination result.

Description

technical field [0001] The invention relates to a multi-core processor system, a control program and a control method for storing data in a memory. Background technique [0002] Conventionally, when a CPU (Central Processing Unit: central processing unit) has a cache with a faster access speed than a memory, when a data write request is generated from the CPU, the data is stored in the cache. Thereby, the CPU can read data from the cache memory, so the speed of data reading can be increased. [0003] In a multi-core processor system, which CPU each thread is allocated to depends on the allocation status, so if there is data shared among multiple threads in the target program, the data may be used by multiple CPUs. Here, assigning threads to the multi-core processor is, for example, assigning to the CPU with the least load. [0004] Therefore, when a multi-core processor system has distributed caches for each CPU, when a write request for data is generated, the technology o...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G06F12/0808G06F12/0831G06F12/0842G06F9/54
CPCG06F12/0842G06F12/0833G06F12/1072G06F2212/1016G06F2212/1044G06F12/0808G06F9/544G06F12/00G06F12/0811G06F2212/283
Inventor 铃木贵久山下浩一郎山内宏真栗原康志
Owner FUJITSU LTD
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