phase locked loop

Abstract

A PLL comprises a phase frequency detector (PFD), a charge pump, a low pass filter, a voltage-controlled oscillator, a frequency divider, and a switch capacitor cell, wherein the switch capacitor cell comprises a switch and a first capacitor, the switch is provided with a first end, a second end and a control end, the first end of the switch is connected with an output end of the charge pump, the second end of the switch is connected with the low pass filter, one end of the first capacitor is connected with the first end of the switch, the other end of the first capacitor is grounded, and switch control signals are input in the control end of the switch. After the PLL is locked, the switch is disconnected when charging and discharging currents charge and discharge the low pass filter and connected after the charging and discharging. The stability of the PLL is improved.

Description

technical field [0001] The invention relates to a phase-locked loop circuit design technology, in particular to a phase-locked loop. Background technique [0002] With the development of contemporary microelectronics technology, the main frequency and performance of microprocessors and workstation systems have been improved, and higher and higher requirements have been placed on the design of the clock generation circuit of the system. As a common design technique, a phase-locked loop (PLL, PhaseLockedLoop) is widely used in a system-on-chip (SOC, SystemonChip) to form a clock generation circuit. [0003] like figure 1 As shown, the phase-locked loop circuit generally includes a frequency discriminator 10 , a charge pump 20 , a low-pass filter 30 , a voltage-controlled oscillator 40 and a frequency divider 50 . The frequency discriminator 10 is used to detect the frequency difference and phase difference between the input signal Fref and the feedback signal Ffb, and genera...

AI Technical Summary

Problems solved by technology

[0010] When the phase-locked loop is locked, ideally, the frequency and phase of the reference clock Fref and the feedback signal Ffb are consistent, but in practical applications, when the phase-locked loop is locked, the frequencies of the feedback signal Ffb and the reference clock Fref are equal , the phase difference is a small constant value, which will cause fluctuations in the control voltage Vctrl, causing the output signal Fout to generate unwanted spurs, which will affect the stability of the phase-locked loop

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