Submission method of descriptor of network interface card (NIC) based on mixing of PIO (process input output) and DMA (direct memory access)

A network interface card and descriptor technology, applied in the field of high-performance computer high-speed interconnection network, can solve problems such as low startup overhead, transmission bottleneck, limited capacity, etc., to improve submission efficiency and data communication efficiency, capacity expansion, and reduction of startup. delayed effect

Active Publication Date: 2013-06-12
NAT UNIV OF DEFENSE TECH
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

Due to the limitation of hardware resources, the capacity of the hardware send queue is limited, for example, it is fixed to be able to receive 512 8-byte data, which may cause a problem: when the hardware send queue is full and the user process still needs descriptors When writing, the user process needs to query the status of the hardware send queue to determine whether new descriptor dat

Method used

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  • Submission method of descriptor of network interface card (NIC) based on mixing of PIO (process input output) and DMA (direct memory access)
  • Submission method of descriptor of network interface card (NIC) based on mixing of PIO (process input output) and DMA (direct memory access)
  • Submission method of descriptor of network interface card (NIC) based on mixing of PIO (process input output) and DMA (direct memory access)

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Example Embodiment

[0067] Such as image 3 As shown, the implementation steps of the method for submitting the network interface card descriptor of this embodiment are as follows:

[0068] 1) Establish a hardware sending queue for storing descriptors and doorbell data written in PIO in the network interface card, and establish a main memory sending queue for storing descriptors in the main memory; hardware sending queue and main memory sending The read pointers of the queue are maintained by the network interface card, and the write pointers of the hardware sending queue and the main memory sending queue are maintained by the user process;

[0069] 2) Initially generate the descriptor to be sent according to the user's communication request, and the type of the initialized generated descriptor is a normal descriptor without data or an immediate descriptor with data;

[0070] 3) Determine the type of the descriptor to be sent. If the descriptor to be sent is an immediate descriptor, write it to the hard...

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Abstract

The invention discloses a submission method of a descriptor of an NIC based on mixing of PIO and DMA. The implementation steps are as follows: 1) a hardware transmit queue is built in an NIC, and a main store transmit queue is built in a main store; 2) a descriptor is initialized; and 3) a consumer process accesses the NIC directly to write the descriptor into the hardware transmit queue directly in a PIO manner, or the descriptor is submitted to the main transmit queue, while door-bell data is written into the hardware transmit queue; when the NIC processes the data of the hardware transmit queue sequentially, current data type is judged, if the current data is the descriptor, and read-back processing is performed from the hardware transmit queue according to the value of a length field; and if the current data is the door-bell data, the current data is retaken and then processed from the main store transmit queue, and a process that the NIC implements the DMA to read a next descriptor and a process of processing the current descriptor are overlapped. The submission method has the advantages that the message start delay is small, the capacity of the transmit queue is large, and data are processed simply and efficiently.

Description

Technical field [0001] The invention relates to the field of high-performance computer high-speed interconnection networks, in particular to a method for submitting network interface card descriptors based on a mixture of PIO and DMA. Background technique [0002] High-performance computers are connected to a large number of main processor nodes (hereinafter referred to as nodes), such as computing nodes, storage nodes, and dedicated processing nodes. Any one of these nodes can be used as an end node, which is defined here as a device that generates or ultimately consumes messages in a high-performance computer. Each node includes a network interface card (NIC), which connects the node to a high-speed interconnection network. The NIC and the nodes are connected by a general I / O bus such as a PCIE bus. [0003] The user process of the node interacts with the NIC through the port to complete various user-level communication operations. The port uses queue pairs to send and receive...

Claims

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Application Information

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IPC IPC(8): G06F13/28H04L12/863
Inventor 徐炜遐刘路王永庆沈胜宇曹继军张鹤颖张磊肖灿文庞征斌王克非伍楠戴艺高蕾
Owner NAT UNIV OF DEFENSE TECH
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